Peripherals/BuiltinRam: Fixed high impedance warning in yosys
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@ -47,6 +47,11 @@
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`define L1_CACHE_SIZE 4
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// Use high impedance instead of some other undefined value
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// when a signal is invalid (for example a data port when a
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// memory is not selected). This could be used for debug
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//`define USE_HIGH_IMPEDANCE
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/********** Internal **********/
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`ifdef SYNTHESIS
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`undef DEBUG_REG_WRITES
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@ -53,10 +53,13 @@ initial begin
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end
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assign cpu_read_data[7:0] = !address[0:0] & !rd & !cs ? memory[address[ADDRESS_WIDTH-1:1]][15:8] : 8'hz;
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assign cpu_read_data[15:8] = !BHE & !rd & !cs ? memory[address[ADDRESS_WIDTH-1:1]][ 7:0] : 8'hz;
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`ifdef USE_HIGH_IMPEDANCE
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assign cpu_read_data[7:0] = !address[0:0] & !rd & !cs ? memory[address[ADDRESS_WIDTH-1:1]][15:8] : `16'hz;
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assign cpu_read_data[15:8] = !BHE & !rd & !cs ? memory[address[ADDRESS_WIDTH-1:1]][ 7:0] : `16'hz;
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`else
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assign cpu_read_data[7:0] = memory[address[ADDRESS_WIDTH-1:1]][15:8];
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assign cpu_read_data[15:8] = memory[address[ADDRESS_WIDTH-1:1]][ 7:0];
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`endif
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always @(posedge clock) begin
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