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Peripherals/BuiltinRam: Fixed high impedance warning in yosys

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This commit is contained in:
(Tim) Efthimis Kritikos 2023-12-04 17:04:22 +00:00
parent 374b1946e9
commit 8c921380bc
2 changed files with 12 additions and 4 deletions
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5
system/config.v
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@ -47,6 +47,11 @@
`define L1_CACHE_SIZE 4 `define L1_CACHE_SIZE 4
// Use high impedance instead of some other undefined value
// when a signal is invalid (for example a data port when a
// memory is not selected). This could be used for debug
//`define USE_HIGH_IMPEDANCE
/********** Internal **********/ /********** Internal **********/
`ifdef SYNTHESIS `ifdef SYNTHESIS
`undef DEBUG_REG_WRITES `undef DEBUG_REG_WRITES

11
system/memory.v
View File

@ -53,10 +53,13 @@ initial begin
end end
`ifdef USE_HIGH_IMPEDANCE
assign cpu_read_data[7:0] = !address[0:0] & !rd & !cs ? memory[address[ADDRESS_WIDTH-1:1]][15:8] : 8'hz; assign cpu_read_data[7:0] = !address[0:0] & !rd & !cs ? memory[address[ADDRESS_WIDTH-1:1]][15:8] : `16'hz;
assign cpu_read_data[15:8] = !BHE & !rd & !cs ? memory[address[ADDRESS_WIDTH-1:1]][ 7:0] : `16'hz;
assign cpu_read_data[15:8] = !BHE & !rd & !cs ? memory[address[ADDRESS_WIDTH-1:1]][ 7:0] : 8'hz; `else
assign cpu_read_data[7:0] = memory[address[ADDRESS_WIDTH-1:1]][15:8];
assign cpu_read_data[15:8] = memory[address[ADDRESS_WIDTH-1:1]][ 7:0];
`endif
always @(posedge clock) begin always @(posedge clock) begin