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Updated versions in README.md

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(Tim) Efthimis Kritikos 2025-10-25 22:09:07 +01:00
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@ -20,11 +20,11 @@ A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisati
Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [./common.mk](./common.mk).
This list shows the software needed and the versions used during development :
* Icarus Verilog : version 12.0 OR **(preferred)** Verilator : 5.018
* Icarus Verilog : version 12.0 OR **(preferred)** Verilator : 5.028
* bin86 : 0.16.21
* GNU Make : 4.4.1
* xxd : 2023-10-25
* POSIX coreutils : GNU coreutils 9.4
* xxd : 2025-08-08
* POSIX coreutils : GNU coreutils 9.8
After that you can run `make` on the top level directory and it should build everything and start the simulation
@ -33,7 +33,7 @@ You need to set FPGA\_BOARD in [./common.mk](./common.mk) to the name of a direc
These are the currently supported FPGA boards:
* OrangeCrab r0.2.1
* OrangeCrab r0.2.1 ( last tested with commit fde181aa66 )
This list shows the software needed and the versions used during development :
@ -45,8 +45,8 @@ This list shows the software needed and the versions used during development :
Additionally, for ECP5 FPGAs:
* prjtrellis : 1.4 ( database commit 4dda149b9e4f1753ebc8b011ece2fe794be1281a )
* nextpnr : 0.6
* prjtrellis : 1.4 ( database commit 015e0330630d7c238c0e4f2cdd9c8157eb78c54a )
* nextpnr : 0.9
Additionally, for FPGAs using the [foboot](https://github.com/im-tomu/foboot) bootloader