Fixed some relatively low hanging fruit in regards to synthesisability
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934e2f5a36
commit
85bdf9f87e
25
system/biu.v
25
system/biu.v
@ -89,19 +89,6 @@ wire [`L1_CACHE_SIZE-1:0] FIFO_SIZE = FIFO_end-FIFO_start;
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reg [3:0] biu_state;
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reg sane;
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always @(negedge reset) begin
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biu_state <= `BIU_HALT;
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write <= 1;
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sane <= 0;
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end
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always @(posedge reset) begin
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biu_state <= `BIU_RESET1;
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/* verilator lint_off BLKSEQ */
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FIFO_start = `L1_CACHE_SIZE'b0;
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FIFO_end = `L1_CACHE_SIZE'b0;
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/* verilator lint_on BLKSEQ */
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end
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reg jump_req_latch;
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reg func;
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@ -111,7 +98,16 @@ reg [19:0]DATA_ADDRESS;
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assign external_address_bus= func ? INSTRUCTION_ADDRESS : DATA_ADDRESS ;
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always @(posedge clock) begin
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if ( jump_req_latch ) begin
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if ( reset == 0 ) begin
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biu_state <= `BIU_HALT;
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write <= 1;
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sane <= 0;
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biu_state <= `BIU_RESET1;
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/* verilator lint_off BLKSEQ */
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FIFO_start = `L1_CACHE_SIZE'b0;
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FIFO_end = `L1_CACHE_SIZE'b0;
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/* verilator lint_on BLKSEQ */
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end else if ( jump_req_latch ) begin
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INSTRUCTION_ADDRESS <= { 4'b0 , ADDRESS_INPUT };
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INSTRUCTION_LOCATION <= ADDRESS_INPUT;
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func <= 1;
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@ -401,7 +397,6 @@ always @( posedge jump_req ) begin
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FIFO_start = FIFO_end ;
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/* verilator lint_on BLKSEQ */
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jump_req_latch <= 1;
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VALID_INSTRUCTION <= 0;
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end
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endmodule
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@ -270,8 +270,8 @@ wire [`UCODE_DATA_BITS-1:0] ucode_data;
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microcode ucode(seq_addr_input,ucode_data);
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`define invalid_instruction next_state=`EXEC_WAIT;ERROR<=`ERR_UNIMPL_INSTRUCTION;IN_MOD=3'b011;seq_addr_entry<=`UCODE_NO_INSTRUCTION;
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`define unimpl_addressing_mode next_state=`EXEC_WAIT;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE;IN_MOD=3'b011;seq_addr_entry<=`UCODE_NO_INSTRUCTION;
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`define invalid_instruction next_state=`EXEC_WAIT;ERROR<=`ERR_UNIMPL_INSTRUCTION;HALT<=0;IN_MOD=3'b011;seq_addr_entry<=`UCODE_NO_INSTRUCTION;opcode_size=0;DEPENDS_ON_PREVIOUS<=0;
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`define unimpl_addressing_mode next_state=`EXEC_WAIT;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE;HALT<=0;IN_MOD=3'b011;seq_addr_entry<=`UCODE_NO_INSTRUCTION;
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//TODO: A possible optimisation for instruction with 8bit parameter and
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@ -833,13 +833,14 @@ always @( FLAGS or INSTRUCTION or SIMPLE_MICRO or seq_addr_input ) begin
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in_alu_sel2=2'b11;
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reg_read_port1_addr={Wbit,3'b000};
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PARAM_ACTION=`LOAD_8;
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MEM_OR_IO=1;
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HALT <= 0;
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PARAM1=0;
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OUT_MOD={3'b000};
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DEPENDS_ON_PREVIOUS<=0;
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IN_MOD=3'b011;
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next_state=`EXEC_WRITE_ENTRY;
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`normal_instruction
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MEM_OR_IO=1;
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end
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11'b1100_1111_???:begin
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/* IRET - Return from interrupt */
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@ -987,6 +988,7 @@ always @( FLAGS or INSTRUCTION or SIMPLE_MICRO or seq_addr_input ) begin
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memio_address_select=ucode_data[39:39];
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MEM_OR_IO=0;
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HALT <= 0;
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ERROR <= 0; //TODO probably, right?
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end
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if(PARAM_ACTION==`LOAD_8)begin
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