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Added 2 more test programs, 2 new instructions and fixed a bug in CMP

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This commit is contained in:
(Tim) Efthimis Kritikos 2023-05-21 01:48:50 +01:00
parent 021dd06e9a
commit 3dd2ff59ea
7 changed files with 224 additions and 87 deletions
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2
Makefile
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@ -21,7 +21,7 @@ VERILATOR_BIN=system/obj_dir/Vsystem
BOOT_CODE=boot_code/brainfuck_mandelbrot.txt BOOT_CODE=boot_code/brainfuck_mandelbrot.txt
GTKWSAVE=./gtkwave_savefile.gtkw GTKWSAVE=./gtkwave_savefile.gtkw
MICROCODE=system/ucode.txt MICROCODE=system/ucode.txt
BOOTABLES=boot_code/brainfuck_compiled.txt boot_code/brainfuck_interpreted.txt boot_code/pipeline_ideal.txt boot_code/fibonacci.txt ${BOOT_CODE} BOOTABLES=boot_code/brainfuck_compiled.txt boot_code/brainfuck_interpreted.txt boot_code/pipeline_ideal.txt boot_code/fibonacci.txt boot_code/gnome_sort.txt boot_code/cache_fill_and_empty.txt ${BOOT_CODE}
NO_ASM=1 NO_ASM=1
include common.mk include common.mk

5
boot_code/Makefile
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@ -1,4 +1,4 @@
SOURCE=brainfuck_interpreted.asm brainfuck_compiled.asm brainfuck_mandelbrot.asm pipeline_ideal.asm fibonacci.asm SOURCE=brainfuck_interpreted.asm brainfuck_compiled.asm brainfuck_mandelbrot.asm pipeline_ideal.asm fibonacci.asm gnome_sort.asm cache_fill_and_empty.asm
BINARIES=$(subst .asm,.txt,${SOURCE}) BINARIES=$(subst .asm,.txt,${SOURCE})
BUILD_FILES=${BINARIES} BUILD_FILES=${BINARIES}
BUILD_FILES+=$(subst .asm,.memdump,${SOURCE}) BUILD_FILES+=$(subst .asm,.memdump,${SOURCE})
@ -12,6 +12,9 @@ brainfuck_interpreted.bin: brainfuck_interpreter_v0.asm hello_9086.bf.asm dos_la
brainfuck_compiled.bin: brainfuck_compiler_v1.asm hello_9086.bf.asm dos_layer.asm brainfuck_compiled.bin: brainfuck_compiler_v1.asm hello_9086.bf.asm dos_layer.asm
brainfuck_mandelbrot.bin: brainfuck_compiler_v1.asm mandelbrot.bf.asm dos_layer.asm brainfuck_mandelbrot.bin: brainfuck_compiler_v1.asm mandelbrot.bf.asm dos_layer.asm
fibonacci.bin: helpers.asm
gnome_sort.bin: helpers.asm
%.bf.asm:%.bf %.bf.asm:%.bf
${Q}sed "s/[a-zA-Z\* ]//g;/^$$/d;s/^/.ASCII '/;s/\$$/'/" "$^" > $@ ${Q}sed "s/[a-zA-Z\* ]//g;/^$$/d;s/^/.ASCII '/;s/\$$/'/" "$^" > $@

38
boot_code/cache_fill_and_empty.asm Normal file
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@ -0,0 +1,38 @@
.ORG 0x0100
mov sp,#STACK
MOV DI,#0x2000
STOS
STOS
STOS
STOS
STOS
STOS
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
MOV CX,#0x0000
HLT
NOTHING: ret
.BLKB 200
STACK:
.ORG 0xFFF0
MOV AX,#0x0100
JMP AX

81
boot_code/fibonacci.asm
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@ -7,13 +7,13 @@ mov sp,#STACK
MOV AX,#0x1 MOV AX,#0x1
MOV BX,#0x1 MOV BX,#0x1
CALL PRINT_HEX CALL PRINT_16_HEX
push bx push bx
MAIN_LOOP: MAIN_LOOP:
pop bx pop bx
CALL PRINT_HEX CALL PRINT_16_HEX
push AX push AX
ADD AX,BX ADD AX,BX
@ -28,84 +28,9 @@ INT #0x21
hlt hlt
;Input AX
PRINT_HEX:
PUSH DX
TEST AH,#0xF0
jz NOT_FIRST_NIBBLE
MOV DL,AH
CALL PRINT_HIGH
JMP SKIP1
NOT_FIRST_NIBBLE:
TEST AH,#0x0F
jz NOT_SECOND_NIBBLE
SKIP1:
MOV DL,AH
CALL PRINT_LOW
JMP SKIP2
NOT_SECOND_NIBBLE:
TEST AL,#0xF0
jz NOT_THIRD_NIBBLE
SKIP2:
MOV DL,AL
CALL PRINT_HIGH
NOT_THIRD_NIBBLE:
MOV DL,AL
CALL PRINT_LOW
PUSH AX
MOV AH,#0x02
MOV DL,#0x20
INT #0x21
POP AX
POP DX
RET
PRINT_HIGH:
AND DL,#0xF0
TEST DL,#0x80
jz NOT1
OR DL,#0x08
NOT1:
TEST DL,#0x40
jz NOT2
OR DL,#0x04
NOT2:
TEST DL,#0x20
jz NOT3
OR DL,#0x02
NOT3:
TEST DL,#0x10
jz DONE
OR DL,#0x01
DONE:
PRINT_LOW:
PUSH AX
AND DL,#0x0F
CMP DL,#0x0A
JNS LETTERS
ADD DL,#0x30
MOV AH,#0x02
INT #0x21
POP AX
RET
LETTERS:
ADD DL,#0x37
MOV AH,#0x02
INT #0x21
POP AX
RET
.BLKB 200 .BLKB 200
STACK: STACK:
INCLUDE helpers.asm
.ORG 0xFFF0 .ORG 0xFFF0
MOV AX,#0x0100 MOV AX,#0x0100

51
boot_code/gnome_sort.asm Normal file
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@ -0,0 +1,51 @@
INCLUDE dos_layer.asm
.org 0x100
mov sp,#STACK
MOV SI,#DATA
GNOME_SORT:
CMP SI,#DATA+7
JZ GNOMED
MOV AX,[SI]
INC SI
CMP AH,AL
JAE GNOME_SORT
SWAP:
MOV BL,AL
MOV AL,AH
MOV AH,BL
DEC SI
MOV [SI],AX
CMP SI,#DATA
JZ GNOME_SORT
DEC SI
JMP GNOME_SORT
GNOMED:
MOV SI,#DATA
PRINT_LOOP:
MOV AL,[SI]
call PRINT_0_8_HEX
INC SI
CMP SI,#DATA+8
JNZ PRINT_LOOP
MOV AH,#0x02
MOV DL,#0x0a
INT #0x21
hlt
DATA: DB 0x51, 0x17, 0x37, 0x5d, 0x06, 0x3f, 0x51, 0x8b
.BLKB 200
STACK:
INCLUDE helpers.asm
.ORG 0xFFF0
MOV AX,#0x0100
JMP AX

93
boot_code/helpers.asm Normal file
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@ -0,0 +1,93 @@
;Input AX
PRINT_16_HEX:
PUSH DX
TEST AH,#0xF0
jz NOT_FIRST_NIBBLE
MOV DL,AH
CALL PRINT_HIGH
JMP SKIP1
NOT_FIRST_NIBBLE:
TEST AH,#0x0F
jz NOT_SECOND_NIBBLE
SKIP1:
MOV DL,AH
CALL PRINT_LOW
JMP SKIP2
NOT_SECOND_NIBBLE:
TEST AL,#0xF0
jz NOT_THIRD_NIBBLE
SKIP2:
MOV DL,AL
CALL PRINT_HIGH
NOT_THIRD_NIBBLE:
MOV DL,AL
CALL PRINT_LOW
PUSH AX
MOV AH,#0x02
MOV DL,#0x20
INT #0x21
POP AX
POP DX
RET
PRINT_HIGH:
AND DL,#0xF0
TEST DL,#0x80
jz NOT1
OR DL,#0x08
NOT1:
TEST DL,#0x40
jz NOT2
OR DL,#0x04
NOT2:
TEST DL,#0x20
jz NOT3
OR DL,#0x02
NOT3:
TEST DL,#0x10
jz DONE
OR DL,#0x01
DONE:
PRINT_LOW:
PUSH AX
AND DL,#0x0F
CMP DL,#0x0A
JNS LETTERS
ADD DL,#0x30
MOV AH,#0x02
INT #0x21
POP AX
RET
LETTERS:
ADD DL,#0x37
MOV AH,#0x02
INT #0x21
POP AX
RET
PRINT_0_8_HEX:
MOV DL,AL
PUSH AX
CALL PRINT_HIGH
POP AX
MOV DL,AL
CALL PRINT_LOW
PUSH AX
MOV AH,#0x02
MOV DL,#0x20
INT #0x21
POP AX
RET

41
system/decoder.v
View File

@ -210,13 +210,16 @@ always @( FLAGS or CIR or SIMPLE_MICRO or seq_addr_input ) begin
/*compare register with param*/ /*compare register with param*/
in_alu_sel2=2'b01; in_alu_sel2=2'b01;
reg_read_port2_addr={Wbit,RM}; reg_read_port2_addr={Wbit,RM};
next_state=`EXEC_DE_LOAD_8_PARAM;
end else begin end else begin
/*compare register indirect access /*compare register indirect access
* with param */ * with param */
in_alu_sel2=2'b00; in_alu_sel2=2'b00;
next_state=`EXEC_DE_LOAD_16_PARAM; /*will then call MEMIO_READ*/ /*will call MEMIO_READ after EXEC_DE_LOAD..*/
end end
if(Wbit)
next_state=`EXEC_DE_LOAD_16_PARAM;
else
next_state=`EXEC_DE_LOAD_8_PARAM;
DEPENDS_ON_PREVIOUS<=0; DEPENDS_ON_PREVIOUS<=0;
`normal_instruction; `normal_instruction;
end end
@ -417,6 +420,7 @@ always @( FLAGS or CIR or SIMPLE_MICRO or seq_addr_input ) begin
else begin else begin
next_state=`EXEC_WRITE_ENTRY; next_state=`EXEC_WRITE_ENTRY;
end end
`normal_instruction;
end end
3'b010: begin 3'b010: begin
/* Jump on (not) Zero */ /* Jump on (not) Zero */
@ -424,6 +428,7 @@ always @( FLAGS or CIR or SIMPLE_MICRO or seq_addr_input ) begin
next_state=`EXEC_NEXT_INSTRUCTION; next_state=`EXEC_NEXT_INSTRUCTION;
else else
next_state=`EXEC_WRITE_ENTRY; next_state=`EXEC_WRITE_ENTRY;
`normal_instruction;
end end
3'b100: begin 3'b100: begin
/* Jump on (not) Sign */ /* Jump on (not) Sign */
@ -431,6 +436,7 @@ always @( FLAGS or CIR or SIMPLE_MICRO or seq_addr_input ) begin
next_state=`EXEC_NEXT_INSTRUCTION; next_state=`EXEC_NEXT_INSTRUCTION;
else else
next_state=`EXEC_WRITE_ENTRY; next_state=`EXEC_WRITE_ENTRY;
`normal_instruction;
end end
3'b101: begin 3'b101: begin
/* Jump on (not) Parity */ /* Jump on (not) Parity */
@ -438,6 +444,7 @@ always @( FLAGS or CIR or SIMPLE_MICRO or seq_addr_input ) begin
next_state=`EXEC_NEXT_INSTRUCTION; next_state=`EXEC_NEXT_INSTRUCTION;
else else
next_state=`EXEC_WRITE_ENTRY; next_state=`EXEC_WRITE_ENTRY;
`normal_instruction;
end end
3'b001: begin 3'b001: begin
/* Jump on (not) Carry */ /* Jump on (not) Carry */
@ -445,12 +452,12 @@ always @( FLAGS or CIR or SIMPLE_MICRO or seq_addr_input ) begin
next_state=`EXEC_NEXT_INSTRUCTION; next_state=`EXEC_NEXT_INSTRUCTION;
else else
next_state=`EXEC_WRITE_ENTRY; next_state=`EXEC_WRITE_ENTRY;
`normal_instruction;
end end
default:begin default:begin
`invalid_instruction; /*We don't support that condition*/ `invalid_instruction; /*We don't support that condition*/
end end
endcase endcase
`normal_instruction;
DEPENDS_ON_PREVIOUS<=1; DEPENDS_ON_PREVIOUS<=1;
memio_address_select=0; memio_address_select=0;
end end
@ -717,13 +724,16 @@ always @( FLAGS or CIR or SIMPLE_MICRO or seq_addr_input ) begin
memio_address_select=0; memio_address_select=0;
`normal_instruction; `normal_instruction;
end end
11'b0000_00??_???:begin 11'b0000_00??_???,11'b0010_10??_???,11'b0011_10??_???:begin
/* CMP - Compare Register/memory and register */
/* 0 0 1 1 1 0 D W | MOD REG R/M | < DISP LO > | < DISP HI > | */
/* SUB - Reg/memory with register to either */
/* 0 0 1 0 1 0 D W | MOD REG R/M | < DISP LO > | < DISP HI > | */
/* ADD - Reg/memory with register to either */ /* ADD - Reg/memory with register to either */
/* 0 0 0 0 0 0 D W | MOD REG R/M | < DISP LO > | < DISP HI > | */ /* 0 0 0 0 0 0 D W | MOD REG R/M | < DISP LO > | < DISP HI > | */
opcode_size=1; opcode_size=1;
Wbit=CIR[8:8]; Wbit=CIR[8:8];
Sbit=0; Sbit=0;
OUT_MOD={1'b0,CIR[7:6]};
IN_MOD=3'b011; IN_MOD=3'b011;
RM=CIR[2:0]; RM=CIR[2:0];
in_alu_sel1=2'b01;//constantly register in_alu_sel1=2'b01;//constantly register
@ -742,9 +752,24 @@ always @( FLAGS or CIR or SIMPLE_MICRO or seq_addr_input ) begin
end end
MEM_OR_IO=0; MEM_OR_IO=0;
memio_address_select=0; memio_address_select=0;
ALU_OP=`ALU_OP_ADD; case (CIR[13:10])
4'b0000: ALU_OP=`ALU_OP_ADD;
4'b1010: ALU_OP=`ALU_OP_SUB;
4'b1110: ALU_OP=`ALU_OP_SUB_REVERSE;
default: begin end
endcase
case (CIR[13:10])
4'b0000: OUT_MOD={1'b0,CIR[7:6]};
4'b1010: OUT_MOD={1'b0,CIR[7:6]};
4'b1110: OUT_MOD=3'b100; /* NULL */
default: begin end
endcase
DEPENDS_ON_PREVIOUS<=0; DEPENDS_ON_PREVIOUS<=0;
`normal_instruction; if(CIR[9:9]==1'b0) begin
`normal_instruction;
end else begin
`unimpl_addressing_mode;
end
end end
default:begin default:begin
`invalid_instruction `invalid_instruction
@ -831,6 +856,8 @@ module InstrSize ( input [10:0] IN, output reg [2:0] VERDICT );
11'b1000_000?_001 : VERDICT <= 3'd3+{2'b0,IN[3:3]}; /* OR - Bitwise OR immediate and register/mem */ 11'b1000_000?_001 : VERDICT <= 3'd3+{2'b0,IN[3:3]}; /* OR - Bitwise OR immediate and register/mem */
11'b1010_100?_??? : VERDICT <= 3'd2+{2'b0,IN[3:3]}; /* TEST - Bitwise AND affecting only flags */ 11'b1010_100?_??? : VERDICT <= 3'd2+{2'b0,IN[3:3]}; /* TEST - Bitwise AND affecting only flags */
11'b0000_00??_??? : VERDICT <= 3'd2; /* ADD - Reg/memory with register to either */ 11'b0000_00??_??? : VERDICT <= 3'd2; /* ADD - Reg/memory with register to either */
11'b0010_10??_??? : VERDICT <= 3'd2; /* SUB - Reg/memory with register to either */
11'b0011_10??_??? : VERDICT <= 3'd2; /* CMP - Compare Register/memory and register */
default:begin end default:begin end
endcase endcase
end end