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Added a POP instruction

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This commit is contained in:
(Tim) Efthimis Kritikos 2023-02-24 11:31:15 +00:00
parent c3580848de
commit 355c673a37
4 changed files with 35 additions and 16 deletions
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19
system/decoder.v
View File

@ -484,6 +484,18 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
endcase
OUT_MOD=3'b100;/*NULL*/
end
11'b0101_1xxx_xxx:begin
/* POP - REG=[SP]; SP+=2 */
/* | 0 1 0 1 1 REG | */
`start_unaligning_instruction
opcode_size=0;
has_operands=0;
Wbit=1;
Sbit=0;
PARAM1=2;
reg_write_addr={1'b1,CIR[10:8]};
seq_addr_entry=`UCODE_POP_ENTRY;
end
default:begin
`invalid_instruction
end
@ -499,7 +511,8 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
2'b10: next_state=`PROC_DE_LOAD_8_PARAM;
2'b11: next_state=`PROC_MEMIO_READ;
endcase
reg_write_addr=ucode_data[11:8 ];
if(ucode_data[35:35]==0)
reg_write_addr=ucode_data[11:8 ];
in_alu1_sel1 =ucode_data[13:12];
in_alu1_sel2 =ucode_data[15:14];
OUT_MOD =ucode_data[18:16];
@ -519,8 +532,8 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
IN_MOD=ucode_data[28:26];
if(ucode_data[34:34]==0)
reg_read_port2_addr=ucode_data[32:29];
if(ucode_data[36:36]==1)
Wbit=ucode_data[35:35];
if(ucode_data[37:37]==1)
Wbit=ucode_data[36:36];
end
end

2
system/processor.v
View File

@ -559,7 +559,7 @@ always @(posedge clock) begin
end else begin
state=`PROC_DE_STATE_ENTRY;
end
reg_write_we=1;
end
default:begin
end

25
system/ucode.txt
View File

@ -22,7 +22,7 @@
//krs: Keep registers, selects weather the register port 1 and/or 2
// addresses is set on that microcoded instruction or kept as it
// was before allowing for registers to be parameterised.
// {Register_port2, Register_port1}
// {Register_write_port,Register_port2, Register_port1}
//
//rr2: reg_read_port2_addr
//
@ -60,21 +60,26 @@
// 36 34 32 28 25 21 18 15 13 11 7 5 0
// CALL
// wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
@001 _00_00_0000_011_1100_001_011__00__01_1100__01_000010 // ALU_1: SP ALU_2: PARAM2 (2) ALU_OP:SUB ALU_out: SP (also fetch the opcode argument to PARAM1)
@002 _00_00_0000_011_zzzz_000_110__10__11_zzzz__00_000011 // ALU_1: 0 ALU_2: PC ALU_OP:ADD ALU_out: [SP]
@003 _00_00_0000_011_zzzz_000_101__10__00_zzzz__00_000000 // ALU_1: PARAM1 (arg) ALU_2: PC ALU_OP:ADD ALU_out: PC
@001 _00_000_0000_011_1100_001_011__00__01_1100__01_000010 // ALU_1: SP ALU_2: PARAM2 (2) ALU_OP:SUB ALU_out: SP (also fetch the opcode argument to PARAM1)
@002 _00_000_0000_011_zzzz_000_110__10__11_zzzz__00_000011 // ALU_1: 0 ALU_2: PC ALU_OP:ADD ALU_out: [SP]
@003 _00_000_0000_011_zzzz_000_101__10__00_zzzz__00_000000 // ALU_1: PARAM1 (arg) ALU_2: PC ALU_OP:ADD ALU_out: PC
// RET
// wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
@004 _00_00_0000_110_zzzz_000_101__00__11_zzzz__11_000101 // ALU_1: 0 ALU_2: PARAM2 ([SP]) ALU_OP:ADD ALU_out: PC (also read [SP] to PARAM2)
@005 _00_00_1100_011_0000_000_011__01__00_1100__00_000000 // ALU_1: PARAM1 (2) ALU_2: SP ALU_OP:ADD ALU_out: SP
@004 _00_000_0000_110_zzzz_000_101__00__11_zzzz__11_000101 // ALU_1: 0 ALU_2: PARAM2 ([SP]) ALU_OP:ADD ALU_out: PC (also read [SP] to PARAM2)
@005 _00_000_1100_011_0000_000_011__01__00_1100__00_000000 // ALU_1: PARAM1 (2) ALU_2: SP ALU_OP:ADD ALU_out: SP
// STOS
// wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
@006 _00_00_1000_011_zzzz_000_000__01__11_zzzz__00_000111 // ALU_1: 0 ALU_2: AX ALU_OP:ADD ALU_out: [DI]
@007 _11_00_zzzz_011_1111_000_011__00__01_1111__00_000000 // ALU_1: DI ALU_2: PARAM2 (2) ALU_OP:ADD ALU_OUT: DI
@006 _00_000_1000_011_zzzz_000_000__01__11_zzzz__00_000111 // ALU_1: 0 ALU_2: AX ALU_OP:ADD ALU_out: [DI]
@007 _11_000_zzzz_011_1111_000_011__00__01_1111__00_000000 // ALU_1: DI ALU_2: PARAM2 (2) ALU_OP:ADD ALU_OUT: DI
// PUSH
// wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
@008 _00_10_0000_011_1100_001_011__00__01_1100__00_001001 // ALU_1: SP ALU_2: PARAM2 (2) ALU_OP:SUB ALU_out: SP (also fetch the opcode argument to PARAM1)
@009 _00_10_0000_011_zzzz_000_110__01__11_zzzz__00_000000 // ALU_1: 0 ALU_2: REG ALU_OP:ADD ALU_out: [SP]
@008 _00_010_0000_011_1100_001_011__00__01_1100__00_001001 // ALU_1: SP ALU_2: PARAM2 (2) ALU_OP:SUB ALU_out: SP (also fetch the opcode argument to PARAM1)
@009 _00_010_0000_011_zzzz_000_110__01__11_zzzz__00_000000 // ALU_1: 0 ALU_2: REG ALU_OP:ADD ALU_out: [SP]
// POP
// wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
@00a _00_100_0000_110_zzzz_011_011__00__11_zzzz__11_001011 // ALU_1: 0 ALU_2: PARAM2 ([SP]) ALU_OP:ADD ALU_out: REG
@00b _00_000_1100_011_0000_000_011__01__00_1100__00_000000 // ALU_1: PARAM1 (2) ALU_2: SP ALU_OP:ADD ALU_out: SP

5
system/ucode_header.v
View File

@ -18,8 +18,8 @@
along with this program. If not, see <http://www.gnu.org/licenses/>. */
`define UCODE_ADDR_BITS 5
`define UCODE_DATA_BITS 37
`define UCODE_SIZE 10
`define UCODE_DATA_BITS 38
`define UCODE_SIZE 12
/* DEFINE ADDRESSES IN THE MICROCODE */
`define UCODE_NO_INSTRUCTION 5'b00000
@ -27,3 +27,4 @@
`define UCODE_RET_ENTRY 5'b00100
`define UCODE_STOS_ENTRY 5'b00110
`define UCODE_PUSH_ENTRY 5'b01000
`define UCODE_POP_ENTRY 5'b01010