Fixed a "combinatorial loop" and now if the build-in memory is reduced the design can be synthesized!
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@ -286,8 +286,10 @@ always @(posedge clock) begin
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end
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endcase
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end
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end
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/**** UPDATE VALID_INSTRUCTION ****/
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/* update VALID_INSTRUCTION and INSTRUCTION */
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always @( posedge clock) begin
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if(jump_req==1)begin
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VALID_INSTRUCTION <= 0;
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@ -76,7 +76,7 @@ wire [`EXEC_STATE_BITS-1:0] next_state;
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wire [`ERROR_BITS-1:0] ERROR;
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instruction_decode instruction_decode(
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/* INPUT */ IF2DE_INSTRUCTION,{8'h0,EX2DE_FLAGS}
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/* INPUT */ IF2DE_INSTRUCTION,{8'h0,EX2DE_FLAGS}, clock
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/* MICROCODE */ ,ucode_seq_addr_entry,SIMPLE_MICRO,ucode_seq_addr
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/* OUTPUT */ ,DEPENDS_ON_PREVIOUS, set_params, MEM_OR_IO,ERROR, HALT
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@ -101,10 +101,8 @@ reg owe_set_init;
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//TODO: Why do we need to make a local copy on a register for the code inside the always @(next_state) to read it?
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// For some reason the raw VALID_INSTRUCTION signal reads always 1 and it has something to do with the block
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// being triggered by next_exec
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reg VALID_INSTRUCTION_lc;
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always @(VALID_INSTRUCTION)begin VALID_INSTRUCTION_lc<=VALID_INSTRUCTION; end
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reg wait_;
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reg [1:0] wait_;
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always @(posedge clock)begin
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if(reset==0)begin
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@ -122,12 +120,7 @@ always @(posedge clock)begin
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VALID_INSTRUCTION_ACK <= 0;
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wait_<=0;
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end else begin
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if(wait_!=0) begin
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set_initial_values <= 0;
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wait_<=0;
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VALID_INSTRUCTION_ACK<=0;
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end else if(next_exec==1'b1)begin
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if ( ( VALID_INSTRUCTION_lc == 1 || SIMPLE_MICRO == 1 ) /*&& DEPENDS_ON_PREVIOUS == 0 && ucode_seq_addr_entry==`UCODE_NO_INSTRUCTION*/) begin
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if(wait_==2) begin
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//`define LATCH(VAR) VAR_LATCHED <= VAR; //TODO would this work?
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IN_MOD_LATCHED <= IN_MOD;
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OUT_MOD_LATCHED <= OUT_MOD;
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@ -183,6 +176,13 @@ always @(posedge clock)begin
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end
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end
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end
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end else if(wait_!=0) begin
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set_initial_values <= 0;
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wait_<=0;
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VALID_INSTRUCTION_ACK<=0;
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end else if(next_exec==1'b1)begin
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if ( ( VALID_INSTRUCTION == 1 || SIMPLE_MICRO == 1 ) /*&& DEPENDS_ON_PREVIOUS == 0 && ucode_seq_addr_entry==`UCODE_NO_INSTRUCTION*/) begin
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wait_<=2;
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end else
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valid_exec_data<=0;
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end else
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@ -225,7 +225,9 @@ assign DATA=ucode_rom[ADDR];
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endmodule
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module instruction_decode(
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/* INPUTS */ input wire [31:0] INSTRUCTION,input wire [15:0] FLAGS
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/* verilator lint_off UNUSEDSIGNAL */
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/* INPUTS */ input wire [31:0] INSTRUCTION,input wire [15:0] FLAGS,input clock
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/* verilator lint_on UNUSEDSIGNAL */
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/* MICROCODE */ ,output reg [`UCODE_ADDR_BITS-1:0] seq_addr_entry, input wire SIMPLE_MICRO, input wire [`UCODE_ADDR_BITS-1:0] seq_addr_input
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/* OUTPUT */ ,output reg DEPENDS_ON_PREVIOUS, output reg set_params,output reg MEM_OR_IO, output reg [`ERROR_BITS-1:0] ERROR, output reg HALT
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@ -272,7 +274,7 @@ reg Sbit,opcode_size;
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// then branching off of that instead of the raw bits. otherwise the code
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// would be identical
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/* verilator lint_off BLKSEQ */
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always @( FLAGS or INSTRUCTION or SIMPLE_MICRO or seq_addr_input ) begin
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always @( posedge clock ) begin
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set_params = 1;
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PARAM_ACTION = `NO_LOAD;
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Sbit=0;//TODO: If no Sbit we assume it's 0,right?
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