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Made the execute unit signal the end of execution by a state change rather than the state of a signal to allow for one cycle instructions

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(Tim) Efthimis Kritikos 2023-05-17 11:05:20 +01:00
parent 53e9d371d7
commit 30c3deca37
3 changed files with 33 additions and 39 deletions
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17
gtkwave_savefile.gtkw
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@ -1,15 +1,15 @@
[*] [*]
[*] GTKWave Analyzer v3.3.111 (w)1999-2020 BSI [*] GTKWave Analyzer v3.3.111 (w)1999-2020 BSI
[*] Tue May 16 11:05:44 2023 [*] Tue May 16 18:44:13 2023
[*] [*]
[dumpfile] "/home/user/9086/system/boot_code.fst" [dumpfile] "/home/user/9086/system/boot_code.fst"
[dumpfile_mtime] "Tue May 16 11:04:39 2023" [dumpfile_mtime] "Tue May 16 18:40:53 2023"
[dumpfile_size] 7259 [dumpfile_size] 205398
[savefile] "/home/user/9086/gtkwave_savefile.gtkw" [savefile] "/home/user/9086/gtkwave_savefile.gtkw"
[timestart] 33090000000 [timestart] 24360000000
[size] 1428 1003 [size] 1140 1003
[pos] -1 -1 [pos] -1 -1
*-32.795048 62150000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-33.095047 38460000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP. [treeopen] TOP.
[treeopen] TOP.system. [treeopen] TOP.system.
[treeopen] TOP.system.p. [treeopen] TOP.system.p.
@ -33,17 +33,16 @@ TOP.system.p.write
- -
@28 @28
TOP.system.p.BIU.VALID_INSTRUCTION TOP.system.p.BIU.VALID_INSTRUCTION
@29
TOP.system.p.valid_instruction_ack TOP.system.p.valid_instruction_ack
@28
TOP.system.p.valid_exec_data TOP.system.p.valid_exec_data
@29
TOP.system.p.execute_unit.next_exec
@22 @22
TOP.system.p.execute_unit.INSTRUCTION_BUFFER[23:0] TOP.system.p.execute_unit.INSTRUCTION_BUFFER[23:0]
TOP.system.p.BIU.biu_state[3:0] TOP.system.p.BIU.biu_state[3:0]
@28 @28
TOP.system.p.execute_unit.exec_state[3:0] TOP.system.p.execute_unit.exec_state[3:0]
TOP.system.p.proc_state[2:0] TOP.system.p.proc_state[2:0]
TOP.system.p.execute_unit.work
TOP.system.p.BIU.write_request TOP.system.p.BIU.write_request
TOP.system.p.BIU.read_request TOP.system.p.BIU.read_request
TOP.system.p.SIMPLE_MICRO TOP.system.p.SIMPLE_MICRO

35
system/execute.v
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@ -20,7 +20,7 @@
module execute_unit ( module execute_unit (
/* GENERAL */ input clock, input reset ,input Wbit, input Sbit, input opcode_size,input [23:0] INSTRUCTION_BUFFER,input valid_input /* GENERAL */ input clock, input reset ,input Wbit, input Sbit, input opcode_size,input [23:0] INSTRUCTION_BUFFER,input valid_input
/* */ ,input [2:0] IN_MOD, input [2:0] OUT_MOD, input memio_address_select, input [15:0] ProgCount, input [2:0] RM, output reg [`ERROR_BITS-1:0] ERROR , input write /*TODO: REMOVE!!*/ /* */ ,input [2:0] IN_MOD, input [2:0] OUT_MOD, input memio_address_select, input [15:0] ProgCount, input [2:0] RM, output reg [`ERROR_BITS-1:0] ERROR , input write /*TODO: REMOVE!!*/
/* */ ,input set_initial_values, output reg work /* */ ,input set_initial_values, output reg next_exec
/* PARAM */ ,input [15:0] PARAM1_INIT, input [15:0] PARAM2_INIT /* PARAM */ ,input [15:0] PARAM1_INIT, input [15:0] PARAM2_INIT
/* STATE CONTROL */ ,output [`EXEC_STATE_BITS-1:0] _exec_state_, input [`EXEC_STATE_BITS-1:0] init_state /* STATE CONTROL */ ,output [`EXEC_STATE_BITS-1:0] _exec_state_, input [`EXEC_STATE_BITS-1:0] init_state
/* ALU CONTROL */ ,input [1:0] in_alu_sel1, input [1:0] in_alu_sel2, input [`ALU_OP_BITS-1:0] ALU_OP, output [15:0] _ALU_O_ /* ALU CONTROL */ ,input [1:0] in_alu_sel1, input [1:0] in_alu_sel2, input [`ALU_OP_BITS-1:0] ALU_OP, output [15:0] _ALU_O_
@ -70,9 +70,8 @@ ALU ALU1(
/*############ Execute logic ########################################################## */ /*############ Execute logic ########################################################## */
always @(posedge valid_input) begin always @(posedge valid_input) begin
if(work == 0)begin if(exec_state == `EXEC_DONE) begin
exec_state <= init_state; exec_state <= init_state;
work <= 1;
reg_write_we <= 1; reg_write_we <= 1;
biu_jump_req <= 0; biu_jump_req <= 0;
use_exec_reg_addr <= 0; use_exec_reg_addr <= 0;
@ -97,13 +96,13 @@ end
always @(posedge clock) begin always @(posedge clock) begin
case (exec_state) case (exec_state)
`EXEC_RESET: begin `EXEC_RESET: begin
work <= 0;
biu_write_request <= 0; biu_write_request <= 0;
biu_read_request <= 0; biu_read_request <= 0;
biu_data_direction <= 0; biu_data_direction <= 0;
biu_jump_req <= 0; biu_jump_req <= 0;
reg_write_we <= 1; reg_write_we <= 1;
exec_state <= `EXEC_DONE; exec_state <= `EXEC_DONE;
next_exec <= 0;
ERROR <= `ERR_NO_ERROR; ERROR <= `ERR_NO_ERROR;
end end
`EXEC_DONE:begin `EXEC_DONE:begin
@ -111,12 +110,9 @@ always @(posedge clock) begin
use_exec_reg_addr <= 0; use_exec_reg_addr <= 0;
if(valid_input)begin if(valid_input)begin
exec_state <= init_state; exec_state <= init_state;
work <= 1; end
end else
work <= 0;
end end
`EXEC_DE_LOAD_REG_TO_PARAM:begin `EXEC_DE_LOAD_REG_TO_PARAM:begin
work <= 1;
PARAM2<=reg_read_port2_data; PARAM2<=reg_read_port2_data;
case(IN_MOD) case(IN_MOD)
3'b000,3'b001,3'b010: exec_state <= `EXEC_MEMIO_READ; 3'b000,3'b001,3'b010: exec_state <= `EXEC_MEMIO_READ;
@ -124,7 +120,6 @@ always @(posedge clock) begin
endcase endcase
end end
`EXEC_DE_LOAD_8_PARAM:begin `EXEC_DE_LOAD_8_PARAM:begin
work <= 1;
if(opcode_size==0)begin if(opcode_size==0)begin
if({Sbit,Wbit}==2'b11)begin if({Sbit,Wbit}==2'b11)begin
/*signed "16bit" read*/ /*signed "16bit" read*/
@ -150,7 +145,6 @@ always @(posedge clock) begin
endcase endcase
end end
`EXEC_DE_LOAD_16_PARAM:begin `EXEC_DE_LOAD_16_PARAM:begin
work <= 1;
if(opcode_size==0)begin if(opcode_size==0)begin
PARAM1[7:0] <= INSTRUCTION_BUFFER[23:16]; PARAM1[7:0] <= INSTRUCTION_BUFFER[23:16];
PARAM1[15:8] <= INSTRUCTION_BUFFER[15:8]; PARAM1[15:8] <= INSTRUCTION_BUFFER[15:8];
@ -164,7 +158,6 @@ always @(posedge clock) begin
endcase endcase
end end
`EXEC_MEMIO_READ:begin `EXEC_MEMIO_READ:begin
work <= 1;
/*Decode MOD R/M, read the data and place it to PARAM1*/ /*Decode MOD R/M, read the data and place it to PARAM1*/
case (IN_MOD) case (IN_MOD)
3'b000, 3'b000,
@ -226,7 +219,6 @@ always @(posedge clock) begin
endcase endcase
end end
`EXEC_MEMIO_READ_SETADDR:begin `EXEC_MEMIO_READ_SETADDR:begin
work <= 1;
if(memio_address_select==0) if(memio_address_select==0)
BIU_ADDRESS_INPUT <= reg_read_port1_data[15:0]; BIU_ADDRESS_INPUT <= reg_read_port1_data[15:0];
else else
@ -243,7 +235,7 @@ always @(posedge clock) begin
end end
end end
`EXEC_NEXT_INSTRUCTION:begin `EXEC_NEXT_INSTRUCTION:begin
work <= 0; next_exec <= !next_exec;
/*necessary for biu to see we went on another state from decode to give us a new instruction*/ /*necessary for biu to see we went on another state from decode to give us a new instruction*/
exec_state <= `EXEC_DONE; exec_state <= `EXEC_DONE;
end end
@ -296,44 +288,40 @@ always @(posedge clock) begin
exec_state <= `EXEC_MEMIO_WRITE; exec_state <= `EXEC_MEMIO_WRITE;
end end
endcase endcase
work <= 1;
end end
3'b011:begin 3'b011:begin
reg_write_we <= 0; reg_write_we <= 0;
exec_state <= `EXEC_DONE; exec_state <= `EXEC_DONE;
work <= 0; next_exec <= !next_exec;
end end
3'b100:begin /*No output*/ 3'b100:begin /*No output*/
exec_state <= `EXEC_DONE; exec_state <= `EXEC_DONE;
work <= 0; next_exec <= !next_exec;
end end
3'b101:begin /* Program Counter*/ 3'b101:begin /* Program Counter*/
BIU_ADDRESS_INPUT <= ALU_O[15:0]; BIU_ADDRESS_INPUT <= ALU_O[15:0];
biu_jump_req <= 1; biu_jump_req <= 1;
exec_state <= `EXEC_JUMP_RELEASE; exec_state <= `EXEC_JUMP_RELEASE;
work <= 1;
end end
3'b110:begin /* SP Indirect write*/ 3'b110:begin /* SP Indirect write*/
reg_read_port1_addr <= 4'b1100; reg_read_port1_addr <= 4'b1100;
use_exec_reg_addr <= 1; use_exec_reg_addr <= 1;
exec_state <= `EXEC_MEMIO_WRITE; exec_state <= `EXEC_MEMIO_WRITE;
work <= 1;
end end
3'b111:begin /* Write to PRAM1 (for microcode calculations) */ 3'b111:begin /* Write to PRAM1 (for microcode calculations) */
PARAM1 <= ALU_O; PARAM1 <= ALU_O;
exec_state <= `EXEC_DONE; exec_state <= `EXEC_DONE;
work <= 0; next_exec <= !next_exec;
end end
default:begin default:begin
`unimpl_addressing_mode `unimpl_addressing_mode
work <= 1;
end end
endcase endcase
end end
`EXEC_JUMP_RELEASE:begin `EXEC_JUMP_RELEASE:begin
biu_jump_req <= 0; biu_jump_req <= 0;
exec_state <= `EXEC_DONE; exec_state <= `EXEC_DONE;
work <= 0; next_exec <= !next_exec;
end end
`EXEC_MEMIO_WRITE:begin `EXEC_MEMIO_WRITE:begin
/* if memio_address_select == 0 ADDRESS: reg_read_port1_data DATA:ALU1_O */ /* if memio_address_select == 0 ADDRESS: reg_read_port1_data DATA:ALU1_O */
@ -349,9 +337,8 @@ always @(posedge clock) begin
if (write == 0) begin //TODO: don't do it that was or better yet don't do it at all somehow if (write == 0) begin //TODO: don't do it that was or better yet don't do it at all somehow
biu_write_request <= 0; biu_write_request <= 0;
exec_state <= `EXEC_DONE; exec_state <= `EXEC_DONE;
work <= 0; next_exec <= !next_exec;
end else end
work <= 1;
end end
`EXEC_HALT:begin `EXEC_HALT:begin

20
system/processor.v
View File

@ -80,11 +80,11 @@ assign OUT_MOD=DE_OUTPUT_sampled[49:47];
wire [`ALU_OP_BITS-1:0] ALU_OP; wire [`ALU_OP_BITS-1:0] ALU_OP;
assign ALU_OP = DE_OUTPUT_sampled[42:40]; assign ALU_OP = DE_OUTPUT_sampled[42:40];
wire work; wire next_exec;
execute_unit execute_unit ( execute_unit execute_unit (
/* GENERAL */ clock, reset, Wbit, Sbit, opcode_size, INSTRUCTION_BUFFER,valid_exec_data /* GENERAL */ clock, reset, Wbit, Sbit, opcode_size, INSTRUCTION_BUFFER,valid_exec_data
/* */ ,IN_MOD, OUT_MOD,memio_address_select, ProgCount, RM, EXEC_ERROR, write /* */ ,IN_MOD, OUT_MOD,memio_address_select, ProgCount, RM, EXEC_ERROR, write
/* */ ,set_initial_values,work /* */ ,set_initial_values,next_exec
/* PARAM */ ,PARAM1_INIT,PARAM2_INIT /* PARAM */ ,PARAM1_INIT,PARAM2_INIT
/* STATE CONTROL */ ,exec_state, next_state /* STATE CONTROL */ ,exec_state, next_state
/* ALU CONTROL */ ,in_alu_sel1, in_alu_sel2, ALU_OP, ALU_O /* ALU CONTROL */ ,in_alu_sel1, in_alu_sel2, ALU_OP, ALU_O
@ -206,6 +206,14 @@ reg [23:0] INSTRUCTION_BUFFER;
reg owe_set_init; reg owe_set_init;
always @(next_exec) begin
valid_exec_data<=0;
proc_state<=`PROC_DE_STATE_ENTRY;
wait_exec<=0;
end
reg wait_exec;
always @(posedge clock) begin always @(posedge clock) begin
case(proc_state) case(proc_state)
`PROC_RESET:begin `PROC_RESET:begin
@ -215,10 +223,11 @@ always @(posedge clock) begin
proc_state <= `PROC_DE_STATE_ENTRY; proc_state <= `PROC_DE_STATE_ENTRY;
owe_set_init <= 0; owe_set_init <= 0;
set_initial_values<=0; set_initial_values<=0;
wait_exec<=0;
end end
`PROC_DE_STATE_ENTRY:begin `PROC_DE_STATE_ENTRY:begin
if( VALID_INSTRUCTION==1 || SIMPLE_MICRO == 1 ) begin if( VALID_INSTRUCTION==1 || SIMPLE_MICRO == 1 ) begin
if(work==0) begin if(wait_exec==0) begin
DE_OUTPUT_sampled <= DE_OUTPUT; DE_OUTPUT_sampled <= DE_OUTPUT;
if(SIMPLE_MICRO==0||owe_set_init==1)begin if(SIMPLE_MICRO==0||owe_set_init==1)begin
@ -251,9 +260,9 @@ always @(posedge clock) begin
SIMPLE_MICRO <= 0; SIMPLE_MICRO <= 0;
end end
end end
wait_exec<=1;
end end
end else begin end else begin
valid_exec_data <= 0;
if( DE_DEPENDS_ON_PREVIOUS == 0 ) if( DE_DEPENDS_ON_PREVIOUS == 0 )
if ( (ucode_seq_addr==`UCODE_NO_INSTRUCTION) && (ucode_seq_addr_entry!=`UCODE_NO_INSTRUCTION) && valid_exec_data==0 )begin if ( (ucode_seq_addr==`UCODE_NO_INSTRUCTION) && (ucode_seq_addr_entry!=`UCODE_NO_INSTRUCTION) && valid_exec_data==0 )begin
/*switch to microcode decoding*/ /*switch to microcode decoding*/
@ -263,8 +272,7 @@ always @(posedge clock) begin
/*keep proc_state the same and rerun decode this time with all the data from the microcode rom*/ /*keep proc_state the same and rerun decode this time with all the data from the microcode rom*/
end end
end end
end else end
valid_exec_data <= 0;
end end
`PROC_HALT:begin `PROC_HALT:begin
end end