Efthimis/9086
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases 1 Wiki Activity

Hadn't added all files to previous commit

Browse Source
This commit is contained in:
(Tim) Efthimis Kritikos 2023-02-10 13:26:23 +00:00
parent 4638346f85
commit 2595dc1b6c
2 changed files with 16 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
cpu/Makefile
View File

@ -14,9 +14,22 @@ wave: ${VVP}
vvp ${VVP} -lxt2 vvp ${VVP} -lxt2
gtkwave test.lx2 gtkwave_savefile.gtkw gtkwave test.lx2 gtkwave_savefile.gtkw
${VVP} : ${SOURCES} ${INCLUDES} ${VVP} : ${SOURCES} ${INCLUDES} boot_code.txt
iverilog -g2012 ${SOURCES} -o $@ iverilog -g2012 ${SOURCES} -o $@
.PHONY: clean .PHONY: clean
clean: clean:
rm -f ${VVP} test.lx2 rm -f ${VVP} test.lx2 boot_code.txt boot_code.bin
boot_code.txt:boot_code.bin
dd if=/dev/zero bs=1 count=256 of=boot_code.stage status=none
dd if=boot_code.bin of=boot_code.stage conv=notrunc,nocreat status=none
xxd -ps -c 2 boot_code.stage > boot_code.txt
rm boot_code.stage
boot_code.bin:boot_code.asm
as86 -0 $< -b $@
.PHONY: dumpas
dumpas: boot_code.bin
objdump -D -b binary -m i8086 boot_code.bin

2
cpu/memory.v
View File

@ -1,5 +1,5 @@
module rom(input [19:0] address,output wire [15:0] data ,input rd,input cs); module rom(input [19:0] address,output wire [15:0] data ,input rd,input cs);
reg [15:0] memory [0:15]; reg [15:0] memory [0:127];
initial begin initial begin
$readmemh("boot_code.txt", memory); $readmemh("boot_code.txt", memory);
end end