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Standardised indentation

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This commit is contained in:
(Tim) Efthimis Kritikos 2023-02-08 12:07:42 +00:00
parent 61a403271c
commit 139ec3c0c0
3 changed files with 122 additions and 122 deletions
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30
cpu/boot_code.txt
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@ -1,17 +1,17 @@
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82
cpu/processor.v
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@ -2,42 +2,42 @@
module clock_gen (input enable, output reg clk);
parameter FREQ = 1000; // in HZ
parameter PHASE = 0; // in degrees
parameter DUTY = 50; // in percentage
parameter FREQ = 1000; // in HZ
parameter PHASE = 0; // in degrees
parameter DUTY = 50; // in percentage
real clk_pd = 1.0/FREQ * 1000000; // convert to ms
real clk_on = DUTY/100.0 * clk_pd;
real clk_off = (100.0 - DUTY)/100.0 * clk_pd;
real quarter = clk_pd/4;
real start_dly = quarter * PHASE/90;
real clk_pd = 1.0/FREQ * 1000000; // convert to ms
real clk_on = DUTY/100.0 * clk_pd;
real clk_off = (100.0 - DUTY)/100.0 * clk_pd;
real quarter = clk_pd/4;
real start_dly = quarter * PHASE/90;
reg start_clk;
reg start_clk;
initial begin
end
initial begin
end
// Initialize variables to zero
initial begin
// Initialize variables to zero
initial begin
clk <= 0;
start_clk <= 0;
end
end
// When clock is enabled, delay driving the clock to one in order
// to achieve the phase effect. start_dly is configured to the
// correct delay for the configured phase. When enable is 0,
// allow enough time to complete the current clock period
always @ (posedge enable or negedge enable) begin
// When clock is enabled, delay driving the clock to one in order
// to achieve the phase effect. start_dly is configured to the
// correct delay for the configured phase. When enable is 0,
// allow enough time to complete the current clock period
always @ (posedge enable or negedge enable) begin
if (enable) begin
#(start_dly) start_clk = 1;
end else begin
#(start_dly) start_clk = 0;
end
end
end
// Achieve duty cycle by a skewed clock on/off time and let this
// run as long as the clocks are turned on.
always @(posedge start_clk) begin
// Achieve duty cycle by a skewed clock on/off time and let this
// run as long as the clocks are turned on.
always @(posedge start_clk) begin
if (start_clk) begin
clk = 1;
@ -48,22 +48,22 @@ module clock_gen (input enable, output reg clk);
clk = 0;
end
end
end
endmodule
module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write);
/* State */
reg [1:0] state;
reg start=0;
reg instruction_finished;
/* State */
reg [1:0] state;
reg start=0;
reg instruction_finished;
/* Registers */
reg [19:0] ProgCount;
/* Registers */
reg [19:0] ProgCount;
/* RESET LOGIC */
always @(negedge reset) begin
/* RESET LOGIC */
always @(negedge reset) begin
if (reset==0) begin
@(posedge clock);
state=0;
@ -71,10 +71,10 @@ module processor ( input clock, input reset , output reg [19:0] external_address
#10
start=1;
end
end
end
/* CLOCK LOGIC */
always @(posedge clock) begin
/* CLOCK LOGIC */
always @(posedge clock) begin
if(instruction_finished) begin
state =0;
end else begin
@ -82,23 +82,23 @@ module processor ( input clock, input reset , output reg [19:0] external_address
state=state+1;
end
end
end
end
always @(state) begin
always @(state) begin
if (state==2) begin
instruction_finished=1;
end else begin
instruction_finished=0;
end
end
end
/* Processor stages */
always @(state) begin
/* Processor stages */
always @(state) begin
if (state==0) begin
external_address_bus <= ProgCount;
read <= 0;
write <= 1;
end
end
end
endmodule

24
cpu/testbench.v
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@ -1,19 +1,19 @@
module tb;
wire clock;
reg reset;
reg clk_enable;
wire [19:0]address_bus;
wire [15:0]data_bus;
wire rd,wr,romcs;
wire clock;
reg reset;
reg clk_enable;
wire [19:0]address_bus;
wire [15:0]data_bus;
wire rd,wr,romcs;
processor p(clock,reset,address_bus,data_bus,rd,wr);
rom bootrom(address_bus,data_bus,rd,romcs);
processor p(clock,reset,address_bus,data_bus,rd,wr);
rom bootrom(address_bus,data_bus,rd,romcs);
clock_gen #(.FREQ(1000)) u1(clk_enable, clock);
clock_gen #(.FREQ(1000)) u1(clk_enable, clock);
assign romcs=0;
assign romcs=0;
initial begin
initial begin
$dumpfile("test.lx2");
$dumpvars(0,p);
clk_enable <= 1;
@ -25,5 +25,5 @@ module tb;
#(10000)
#50 $finish;
end
end
endmodule