Standardised indentation

This commit is contained in:
(Tim) Efthimis Kritikos 2023-02-08 12:07:42 +00:00
parent 61a403271c
commit 139ec3c0c0
3 changed files with 122 additions and 122 deletions

View File

@ -1,17 +1,17 @@
// 0x00000000 // 0x00000000
55AA 55AA
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000

View File

@ -1,104 +1,104 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module clock_gen (input enable, output reg clk); module clock_gen (input enable, output reg clk);
parameter FREQ = 1000; // in HZ parameter FREQ = 1000; // in HZ
parameter PHASE = 0; // in degrees parameter PHASE = 0; // in degrees
parameter DUTY = 50; // in percentage parameter DUTY = 50; // in percentage
real clk_pd = 1.0/FREQ * 1000000; // convert to ms real clk_pd = 1.0/FREQ * 1000000; // convert to ms
real clk_on = DUTY/100.0 * clk_pd; real clk_on = DUTY/100.0 * clk_pd;
real clk_off = (100.0 - DUTY)/100.0 * clk_pd; real clk_off = (100.0 - DUTY)/100.0 * clk_pd;
real quarter = clk_pd/4; real quarter = clk_pd/4;
real start_dly = quarter * PHASE/90; real start_dly = quarter * PHASE/90;
reg start_clk; reg start_clk;
initial begin initial begin
end end
// Initialize variables to zero // Initialize variables to zero
initial begin initial begin
clk <= 0; clk <= 0;
start_clk <= 0; start_clk <= 0;
end end
// When clock is enabled, delay driving the clock to one in order // When clock is enabled, delay driving the clock to one in order
// to achieve the phase effect. start_dly is configured to the // to achieve the phase effect. start_dly is configured to the
// correct delay for the configured phase. When enable is 0, // correct delay for the configured phase. When enable is 0,
// allow enough time to complete the current clock period // allow enough time to complete the current clock period
always @ (posedge enable or negedge enable) begin always @ (posedge enable or negedge enable) begin
if (enable) begin if (enable) begin
#(start_dly) start_clk = 1; #(start_dly) start_clk = 1;
end else begin end else begin
#(start_dly) start_clk = 0; #(start_dly) start_clk = 0;
end end
end end
// Achieve duty cycle by a skewed clock on/off time and let this // Achieve duty cycle by a skewed clock on/off time and let this
// run as long as the clocks are turned on. // run as long as the clocks are turned on.
always @(posedge start_clk) begin always @(posedge start_clk) begin
if (start_clk) begin if (start_clk) begin
clk = 1; clk = 1;
while (start_clk) begin while (start_clk) begin
#(clk_on) clk = 0; #(clk_on) clk = 0;
#(clk_off) clk = 1; #(clk_off) clk = 1;
end end
clk = 0; clk = 0;
end end
end end
endmodule endmodule
module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write); module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write);
/* State */ /* State */
reg [1:0] state; reg [1:0] state;
reg start=0; reg start=0;
reg instruction_finished; reg instruction_finished;
/* Registers */ /* Registers */
reg [19:0] ProgCount; reg [19:0] ProgCount;
/* RESET LOGIC */ /* RESET LOGIC */
always @(negedge reset) begin always @(negedge reset) begin
if (reset==0) begin if (reset==0) begin
@(posedge clock); @(posedge clock);
state=0; state=0;
ProgCount=0;//TODO: Reset Vector ProgCount=0;//TODO: Reset Vector
#10 #10
start=1; start=1;
end end
end end
/* CLOCK LOGIC */ /* CLOCK LOGIC */
always @(posedge clock) begin always @(posedge clock) begin
if(instruction_finished) begin if(instruction_finished) begin
state =0; state =0;
end else begin end else begin
if (clock && start==1) begin if (clock && start==1) begin
state=state+1; state=state+1;
end end
end end
end end
always @(state) begin always @(state) begin
if (state==2) begin if (state==2) begin
instruction_finished=1; instruction_finished=1;
end else begin end else begin
instruction_finished=0; instruction_finished=0;
end end
end end
/* Processor stages */ /* Processor stages */
always @(state) begin always @(state) begin
if (state==0) begin if (state==0) begin
external_address_bus <= ProgCount; external_address_bus <= ProgCount;
read <= 0; read <= 0;
write <= 1; write <= 1;
end end
end end
endmodule endmodule

View File

@ -1,29 +1,29 @@
module tb; module tb;
wire clock; wire clock;
reg reset; reg reset;
reg clk_enable; reg clk_enable;
wire [19:0]address_bus; wire [19:0]address_bus;
wire [15:0]data_bus; wire [15:0]data_bus;
wire rd,wr,romcs; wire rd,wr,romcs;
processor p(clock,reset,address_bus,data_bus,rd,wr); processor p(clock,reset,address_bus,data_bus,rd,wr);
rom bootrom(address_bus,data_bus,rd,romcs); rom bootrom(address_bus,data_bus,rd,romcs);
clock_gen #(.FREQ(1000)) u1(clk_enable, clock);
assign romcs=0; clock_gen #(.FREQ(1000)) u1(clk_enable, clock);
initial begin assign romcs=0;
$dumpfile("test.lx2");
$dumpvars(0,p);
clk_enable <= 1;
#($random%500) initial begin
reset = 0; $dumpfile("test.lx2");
#(100) $dumpvars(0,p);
reset = 1; clk_enable <= 1;
#(10000)
#50 $finish; #($random%500)
end reset = 0;
#(100)
reset = 1;
#(10000)
#50 $finish;
end
endmodule endmodule