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Added definition of the version names to README

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(Tim) Efthimis Kritikos 2023-05-04 03:21:53 +01:00
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A CPU that aims to be binary compatible with the 8086 and with as many optimisations as possible A CPU that aims to be binary compatible with the 8086 and with as many optimisations as possible
### Progress ### Progress
* [X] Executing code
* [X] Is Turing complete * [ ] 8086
* [ ] Can boot up MS-DOS / FreeDOS * [X] Executing code
* [ ] Is completely binary compatible * [X] Is Turing complete
* [ ] Is pipelined * [ ] Can boot up MS-DOS / FreeDOS
* [ ] Is Out of Order * [ ] Is completely binary compatible
* [ ] Is superscalar * [ ] Is pipelined
* [ ] Has been successfully synthesized * [ ] Is Out of Order
* [ ] Is superscalar
* [ ] Has been successfully synthesized
### Simulating it ### Simulating it
Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk) Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk)
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### License ### License
All parts of this project are licensed under the GNU General Public License version 3 or later All parts of this project are licensed under the GNU General Public License version 3 or later
### Versions
The version consist of three numbers:
1. The CPU that this version aims to be compatible with
1. The specific milestone
1. Patch level
For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached.