Removed some code that wasn't meant for synthesis and fixed important bug in Makefile

This commit is contained in:
(Tim) Efthimis Kritikos 2023-11-02 22:19:15 +00:00
parent 601397b7f0
commit 08aac5c7b6
3 changed files with 65 additions and 54 deletions

View File

@ -64,7 +64,7 @@ else
$(error invalid ECP5 device ${ECP5_DEVICE}) $(error invalid ECP5 device ${ECP5_DEVICE})
endif endif
ECP5_TARGETS=synth_ecp5.json synth_ecp5_out.config synth_ecp5.bit synth_ecp5.dfu fpga_config/${FPGA_BOARD}/fpga_top.v ECP5_TARGETS=synth_ecp5.json synth_ecp5_out.config synth_ecp5.bit synth_ecp5.dfu
ECP5_TARGETS+=abc.history # created from yosys ECP5_TARGETS+=abc.history # created from yosys
synth_ecp5.json: ${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ${INCLUDES} boot_code.txt synth_ecp5.json: ${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ${INCLUDES} boot_code.txt

View File

@ -47,6 +47,13 @@
/********** Internal **********/ /********** Internal **********/
`ifdef SYNTHESIS
`undef DEBUG_REG_WRITES
`undef DEBUG_PC_ADDRESS
`undef DEBUG_DATA_READ_WRITES
`undef CALCULATE_IPC
`undef OTUPUT_JSON_STATISTICS
`endif
`ifdef OTUPUT_JSON_STATISTICS `ifdef OTUPUT_JSON_STATISTICS
`define CALCULATE_IPC `define CALCULATE_IPC

View File

@ -102,10 +102,12 @@ always @(negedge clock)begin
end end
`endif `endif
`ifndef SYNTHESIS
always @(negedge wr) begin always @(negedge wr) begin
if(IOMEM==1'b1 && address_bus[7:0]==8'hA5 ) if(IOMEM==1'b1 && address_bus[7:0]==8'hA5 )
$write("%s" ,data_bus_write[15:8]); $write("%s" ,data_bus_write[15:8]);
end end
`endif
`ifdef CALCULATE_IPC `ifdef CALCULATE_IPC
@ -132,7 +134,16 @@ end
`ifdef OTUPUT_JSON_STATISTICS `ifdef OTUPUT_JSON_STATISTICS
reg [128:0] instruction_count_temp; reg [128:0] instruction_count_temp;
`endif `endif
always @(posedge clock) begin
`ifndef SYNTHESIS
reg sane;
reg [128:0] cycles;
always @(posedge reset)begin
sane<=1;
end
always @(posedge clock) begin
/* Allow some clock cycles for the waveform*/ /* Allow some clock cycles for the waveform*/
case(finish) case(finish)
2'd0: begin end 2'd0: begin end
@ -157,18 +168,12 @@ always @(posedge clock) begin
`endif `endif
end end
2'd3: begin 2'd3: begin
`ifndef SYNTHESIS
$finish; $finish;
`endif
end end
endcase endcase
end end
always @(posedge reset)begin always @( ERROR ) begin
sane<=1;
end
reg sane;
always @( ERROR ) begin
if ( ERROR != `ERR_NO_ERROR && sane == 1 ) begin if ( ERROR != `ERR_NO_ERROR && sane == 1 ) begin
$display("PROCESSOR RUN INTO AN ERROR."); $display("PROCESSOR RUN INTO AN ERROR.");
case (ERROR) case (ERROR)
@ -182,16 +187,15 @@ always @( ERROR ) begin
end end
endcase endcase
$display("Cycles run for: %0d",cycles-1); $display("Cycles run for: %0d",cycles-1);
`ifndef SYNTHESIS
if($value$plusargs("MEMDUMP=%s",memdump_name))begin if($value$plusargs("MEMDUMP=%s",memdump_name))begin
$writememh(memdump_name, system.sysmem.memory,0,32767); $writememh(memdump_name, system.sysmem.memory,0,32767);
end end
`endif
finish<=2'd1; finish<=2'd1;
end end
end end
`endif
reg [128:0] cycles;
always @(negedge clock)begin always @(negedge clock)begin
if(reset==1) if(reset==1)