448 lines
12 KiB
Coq
448 lines
12 KiB
Coq
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/* decoder.v - Implementation of instruction opcode decoding logic
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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`include "proc_state_def.v"
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`include "alu_header.v"
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module decoder(
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input wire [15:0] CIR,input wire [15:0] FLAGS, output reg Wbit, output reg Sbit, output reg unaligning ,output reg opcode_size, output reg ERROR,output reg [`PROC_STATE_BITS-1:0]next_state
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,output reg [1:0]MOD, output reg [2:0]RM, output reg [15:0] PARAM1,output reg [15:0] PARAM2,output reg HALT,output reg has_operands
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,output reg [1:0]in_alu1_sel1,output reg [1:0]in_alu1_sel2,output reg [2:0]out_alu1_sel
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,output reg [3:0]reg_read_port1_addr, output reg [3:0]reg_write_addr
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,output reg [2:0]ALU_1OP
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);
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/* 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 */
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`define invalid_instruction next_state=`PROC_IF_STATE_ENTRY;ERROR=1;MOD=2'b11;
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`define start_aligning_instruction unaligning=0;
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`define start_unaligning_instruction unaligning=1;
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always @( CIR ) begin
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ERROR=0;HALT=0;
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MOD=2'b11;/*TODO:remove*/
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case(CIR[15:10])
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6'b000001 : begin
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/* ADD, ... */
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if ( CIR[9:9] == 0 )begin
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/* Add Immediate word/byte to accumulator */
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/* 0 0 0 0 0 1 0 W | DATA | DATA if W |*/
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opcode_size=0;
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has_operands=1;
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Wbit=CIR[8:8];
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if(Wbit)
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`start_unaligning_instruction
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else
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`start_aligning_instruction
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MOD=2'b11;
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in_alu1_sel1=2'b00;
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in_alu1_sel2=2'b01;
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out_alu1_sel=3'b011;
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reg_read_port1_addr={CIR[8:8],3'b000};
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reg_write_addr={CIR[8:8],3'b000};
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ALU_1OP=`ALU_OP_ADD;
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if(CIR[8:8]==1)
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next_state=`PROC_DE_LOAD_16_PARAM;
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else begin
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PARAM1[7:0]=CIR[7:0];
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next_state=`PROC_EX_STATE_ENTRY;
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end
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end else begin
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`invalid_instruction
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end
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end
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6'b100000 : begin
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/* ADD, ADC, SUB, SBB, CMP , AND, ... */
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case (CIR[5:3])
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3'b000 : begin
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/* Add Immediate word/byte to register/memory */
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/* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
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opcode_size=1;
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has_operands=1;
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`start_aligning_instruction
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Wbit=CIR[8:8];
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MOD=2'b11;
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in_alu1_sel1=2'b00;
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in_alu1_sel2=2'b01;
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out_alu1_sel={1'b0,CIR[7:6]};
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reg_read_port1_addr={CIR[8:8],CIR[2:0]};
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reg_write_addr={CIR[8:8],CIR[2:0]};
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ALU_1OP=`ALU_OP_ADD;
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next_state=`PROC_DE_LOAD_16_PARAM;
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if(CIR[8:8]==1)
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next_state=`PROC_DE_LOAD_16_PARAM;
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else begin
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`invalid_instruction /*do 8bit loads*/
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end
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end
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3'b111 : begin
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/* CMP - compare Immediate with register / memory */
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/* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
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opcode_size=1;
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has_operands=1;
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Wbit=CIR[8:8];
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Sbit=CIR[9:9];
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MOD=CIR[7:6];
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if((Wbit==1)&&(CIR[9:9]==1))begin
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`start_unaligning_instruction
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end else begin
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`invalid_instruction;
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end
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if(MOD==2'b11)begin
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in_alu1_sel1=2'b00;
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in_alu1_sel2=2'b01;
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reg_read_port1_addr={CIR[8:8],CIR[2:0]};
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out_alu1_sel=3'b100;
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ALU_1OP=`ALU_OP_SUB;
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next_state=`PROC_DE_LOAD_8_PARAM;
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end else begin
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`invalid_instruction
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end
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end
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default:begin
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`invalid_instruction
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end
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endcase
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end
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6'b101100,
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6'b101101:begin
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/* MOV - Move Immediate byte to register */
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/* 1 0 1 1 W REG | DATA | DATA if W |*/
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has_operands=1;
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Wbit=CIR[11:11];
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opcode_size=0;
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if(Wbit)
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`start_unaligning_instruction
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else
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`start_aligning_instruction
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MOD=2'b11;
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in_alu1_sel1=2'b00;
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in_alu1_sel2=2'b00;
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out_alu1_sel=3'b011;
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reg_write_addr={1'b0,CIR[10:8]};
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PARAM1[7:0]=CIR[7:0];
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PARAM2=0;
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ALU_1OP=`ALU_OP_ADD;
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next_state=`PROC_EX_STATE_ENTRY;
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end
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6'b101110,
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6'b101111 : begin
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/*MOV - Move Immediate word to register*/
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has_operands=1;
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Wbit=CIR[11:11];
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opcode_size=0;
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if(Wbit)
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`start_unaligning_instruction
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else
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`start_aligning_instruction
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MOD=2'b11;
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in_alu1_sel1=2'b00;
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in_alu1_sel2=2'b00;
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out_alu1_sel=3'b011;
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reg_write_addr={1'b1,CIR[10:8]};
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ALU_1OP=`ALU_OP_ADD;
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PARAM2=0;
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next_state=`PROC_DE_LOAD_16_PARAM;
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end
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6'b100010 : begin
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/* MOV - Reg/Mem to/from register */
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/* 1 0 0 0 1 0 D W | MOD REG RM | < DISP LO > | < DISP HI > |*/
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has_operands=0;
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`start_aligning_instruction
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opcode_size=1;
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MOD=CIR[7:6];
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RM=CIR[2:0];
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Wbit=CIR[8:8];
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in_alu1_sel2=2'b00;
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if(CIR[9:9] == 1)begin
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/* Mem/Reg to reg */
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if(MOD==2'b11)begin
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/*Reg to Reg*/
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in_alu1_sel1=2'b01;
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reg_read_port1_addr=CIR[2:0];
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next_state=`PROC_EX_STATE_ENTRY;
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end else begin
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/*Mem to Reg*/
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in_alu1_sel1=2'b00;
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next_state=`RPOC_MEMIO_READ;
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end
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out_alu1_sel=3'b011;
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reg_write_addr={Wbit,CIR[5:3]};
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end else begin
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/* Reg to Mem/Reg */
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if(MOD==2'b11)begin
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/*Reg to Reg*/
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in_alu1_sel1=2'b01;
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out_alu1_sel=3'b011;
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reg_write_addr={Wbit,CIR[2:0]};
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next_state=`PROC_EX_STATE_ENTRY;
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end else begin
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/*Reg to Mem*/
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in_alu1_sel1=2'b00;
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reg_read_port1_addr=CIR[5:3];
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out_alu1_sel={1'b0,MOD};
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next_state=`PROC_DE_LOAD_REG_TO_PARAM;
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end
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reg_read_port1_addr={Wbit,CIR[5:3]};
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end
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ALU_1OP=`ALU_OP_ADD;
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PARAM2=0;
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end
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6'b010000,//INC
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6'b010001,//INC
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6'b010010,//DEC
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6'b010011:begin//DEC
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/* DEC - Decrement Register */
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/* | 0 1 0 0 1 REG | */
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/* INC - Increment Register */
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/* | 0 1 0 0 0 REG | */
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has_operands=0;
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opcode_size=0;
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`start_unaligning_instruction
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Wbit=1;
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in_alu1_sel1=2'b01;
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in_alu1_sel2=2'b00;
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out_alu1_sel=3'b011;
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MOD=2'b11;
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PARAM2=1;
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reg_read_port1_addr={1'b1,CIR[10:8]};
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reg_write_addr={1'b1,CIR[10:8]};
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if(CIR[11:11]==0)
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ALU_1OP=`ALU_OP_ADD;
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else
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ALU_1OP=`ALU_OP_SUB;
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next_state=`PROC_EX_STATE_ENTRY;
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end
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6'b111111 : begin
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/* INC */
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if (CIR[9:9] == 1 ) begin
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case (CIR[5:3])
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3'b000,3'b001 :begin
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/* INC - Register/Memory */
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/* 1 1 1 1 1 1 1 W | MOD 0 0 0 R/M | < DISP LO> | < DISP HI> */
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/* DEC - Register/Memory */
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/* 1 1 1 1 1 1 1 W | MOD 0 0 1 R/M | < DISP LO> | < DISP HI> */
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has_operands=1;
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opcode_size=1;
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`start_aligning_instruction
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Wbit=CIR[8:8];
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MOD=CIR[7:6];
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RM=CIR[2:0];
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in_alu1_sel1=(MOD==2'b11)? 2'b01 : 2'b00;
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in_alu1_sel2=2'b00;/* number 1 */
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out_alu1_sel={1'b0,MOD};
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PARAM2=1;
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/*in case MOD=11 */
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reg_read_port1_addr={1'b0,RM};
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reg_write_addr={1'b0,RM};
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ALU_1OP=(CIR[3:3]==1)?`ALU_OP_SUB:`ALU_OP_ADD;
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if ( CIR[7:6] == 2'b11 )
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next_state=`PROC_EX_STATE_ENTRY;
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else
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next_state=`RPOC_MEMIO_READ;
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end
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default:begin
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`invalid_instruction
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end
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endcase
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end else begin
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`invalid_instruction
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end
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end
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6'b111101 : begin
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/*HLT, CMC, TEST, NOT, NEG, MUL, IMUL, .... */
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case (CIR[9:8])
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2'b00:begin
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/* HLT - Halt */
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/* 1 1 1 1 0 1 0 0 | */
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has_operands=0;
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opcode_size=0;
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`start_unaligning_instruction
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MOD=2'b11;
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HALT=1;
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next_state=`PROC_HALT_STATE;
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end
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default:begin
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`invalid_instruction;
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end
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endcase
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end
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6'b001111 : begin
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if ( CIR[9:9] == 0 ) begin
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/* CMP - Compare Immediate with accumulator */
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/* 0 0 1 1 1 1 0 W | DATA | DATA if W |*/
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/* */
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/* NOTE: 8086 doc doesn't show the third byte but the */
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/* W flag and my assembler seem to disagree */
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Wbit=CIR[8:8];
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opcode_size=0;
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has_operands=1;
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if(Wbit)
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`start_unaligning_instruction
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else
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`start_aligning_instruction
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MOD=2'b11;
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in_alu1_sel1=2'b00;
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in_alu1_sel2=2'b01;
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reg_read_port1_addr={CIR[8:8],3'b000};
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out_alu1_sel=3'b100;
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ALU_1OP=`ALU_OP_SUB;
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if(CIR[8:8]==1)
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next_state=`PROC_DE_LOAD_16_PARAM;
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else begin
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PARAM1[7:0]=CIR[7:0];
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next_state=`PROC_EX_STATE_ENTRY;
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end
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end else begin
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`invalid_instruction
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end
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end
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6'b011100,
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6'b011101,
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6'b011110,
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6'b011111:begin
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/* Conditional relative jumps */
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/* JE/JZ - Jump on Zero */
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/* 0 1 1 1 0 1 0 0 | IP-INC8 |*/
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/* JS - Jump on Sign */
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/* 0 1 1 1 1 0 0 0 | IP-INC8 |*/
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/* JNS -Jump on not Sign */
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/* 0 1 1 1 1 0 0 1 | IP-INC8 |*/
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/* .... */
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has_operands=1;
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`start_aligning_instruction
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Wbit=1;
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opcode_size=0;
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in_alu1_sel1=2'b10;
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in_alu1_sel2=2'b00;
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PARAM2={{8{CIR[7:7]}},CIR[7:0]};
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ALU_1OP=`ALU_OP_ADD_SIGNED_B;
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out_alu1_sel=3'b101;
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case(CIR[11:9])
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4'b000: begin
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/* Jump on (not) Overflow */
|
||
|
|
if(FLAGS[11:11]==CIR[8:8])
|
||
|
|
next_state=`PROC_IF_STATE_ENTRY;
|
||
|
|
else begin
|
||
|
|
next_state=`PROC_EX_STATE_ENTRY;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
4'b010: begin
|
||
|
|
/* Jump on (not) Zero */
|
||
|
|
if(FLAGS[6:6]==CIR[8:8])
|
||
|
|
next_state=`PROC_IF_STATE_ENTRY;
|
||
|
|
else
|
||
|
|
next_state=`PROC_EX_STATE_ENTRY;
|
||
|
|
end
|
||
|
|
4'b100: begin
|
||
|
|
/* Jump on (not) Sign */
|
||
|
|
if(FLAGS[7:7]==CIR[8:8])
|
||
|
|
next_state=`PROC_IF_STATE_ENTRY;
|
||
|
|
else
|
||
|
|
next_state=`PROC_EX_STATE_ENTRY;
|
||
|
|
end
|
||
|
|
4'b101: begin
|
||
|
|
/* Jump on (not) Parity */
|
||
|
|
if(FLAGS[2:2]==CIR[8:8])
|
||
|
|
next_state=`PROC_IF_STATE_ENTRY;
|
||
|
|
else
|
||
|
|
next_state=`PROC_EX_STATE_ENTRY;
|
||
|
|
end
|
||
|
|
default:begin
|
||
|
|
`invalid_instruction; /*We don't support that condition*/
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
6'b111010:begin
|
||
|
|
/* JMP,CALL */
|
||
|
|
case(CIR[9:8])
|
||
|
|
2'b00: begin
|
||
|
|
/* CALL - Call direct within segment */
|
||
|
|
/* 1 1 1 0 1 0 0 0 | IP-INC-LO | IP-INC-HI |*/
|
||
|
|
`invalid_instruction
|
||
|
|
end
|
||
|
|
2'b01: begin
|
||
|
|
/* JMP - Uncoditional Jump direct within segment */
|
||
|
|
/* 1 1 1 0 1 0 0 1 | IP-INC-LO | IP-INC-HI |*/
|
||
|
|
`invalid_instruction
|
||
|
|
end
|
||
|
|
2'b10: begin
|
||
|
|
/* JMP - Unconditional jump direct intersegment */
|
||
|
|
/* 0 0 0 0 0 0 0 0 | IP-LO | IP-HI | CS-LO | CS-HI | */
|
||
|
|
`invalid_instruction
|
||
|
|
end
|
||
|
|
2'b11: begin
|
||
|
|
/* JMP - Unconditional jump direct within segment (short) */
|
||
|
|
/* | 1 1 1 0 1 0 0 1 | IP-INC-LO | */
|
||
|
|
`start_aligning_instruction
|
||
|
|
opcode_size=0;
|
||
|
|
has_operands=1;
|
||
|
|
Wbit=1;
|
||
|
|
in_alu1_sel1=2'b10;
|
||
|
|
in_alu1_sel2=2'b00;
|
||
|
|
PARAM2={{8{CIR[7:7]}},CIR[7:0]};
|
||
|
|
ALU_1OP=`ALU_OP_ADD_SIGNED_B;
|
||
|
|
out_alu1_sel=3'b101;
|
||
|
|
next_state=`PROC_EX_STATE_ENTRY;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
6'b110011:begin
|
||
|
|
case(CIR[9:8])
|
||
|
|
2'b00:begin
|
||
|
|
`invalid_instruction
|
||
|
|
end
|
||
|
|
2'b01:begin
|
||
|
|
if(CIR[7:0]==8'h21) begin
|
||
|
|
/* INT - execut interrupt handler */
|
||
|
|
/* 1 1 0 0 1 1 0 1 | DATA |*/
|
||
|
|
has_operands=1;
|
||
|
|
opcode_size=0;
|
||
|
|
`start_aligning_instruction
|
||
|
|
/* Emulate MS-DOS print routines */
|
||
|
|
$write("%s" ,register_file.registers[2][7:0]); /*TODO:Could trigger erroneously while CIR is not final*/
|
||
|
|
next_state=`PROC_IF_STATE_ENTRY;
|
||
|
|
end else begin
|
||
|
|
`invalid_instruction
|
||
|
|
end
|
||
|
|
end
|
||
|
|
2'b10:begin
|
||
|
|
`invalid_instruction
|
||
|
|
end
|
||
|
|
2'b11:begin
|
||
|
|
`invalid_instruction
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
default:begin
|
||
|
|
`invalid_instruction
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
endmodule
|