2023-02-19 00:52:52 +00:00
|
|
|
<img width="186" height="70" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_design1.svg">
|
2023-02-19 00:20:53 +00:00
|
|
|
|
2023-02-08 08:38:10 +00:00
|
|
|
|
2023-05-23 15:18:33 +00:00
|
|
|
A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.
|
2023-02-10 13:27:15 +00:00
|
|
|
|
|
|
|
|
### Progress
|
2023-05-04 02:21:53 +00:00
|
|
|
|
|
|
|
|
* [ ] 8086
|
|
|
|
|
* [X] Executing code
|
|
|
|
|
* [X] Is Turing complete
|
|
|
|
|
* [ ] Can boot up MS-DOS / FreeDOS
|
|
|
|
|
* [ ] Is completely binary compatible
|
2023-05-13 05:51:35 +00:00
|
|
|
* [X] Is pipelined
|
2023-05-04 02:21:53 +00:00
|
|
|
* [ ] Is Out of Order
|
|
|
|
|
* [ ] Is superscalar
|
|
|
|
|
* [ ] Has been successfully synthesized
|
2023-02-10 13:27:15 +00:00
|
|
|
|
2023-02-19 00:52:52 +00:00
|
|
|
### Simulating it
|
2023-03-05 06:37:07 +00:00
|
|
|
Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk)
|
2023-03-06 21:57:36 +00:00
|
|
|
Specifically this list shows the software needed and the versions used during development (other versions should work as well)
|
2023-02-10 13:27:15 +00:00
|
|
|
|
2023-10-21 17:38:35 +00:00
|
|
|
* Icarus Verilog : version 12.0 OR **(preferred)** Verilator : 5.016
|
2023-03-05 06:37:07 +00:00
|
|
|
* bin86 : 0.16.21
|
|
|
|
|
* GNU Make : 4.4.1
|
|
|
|
|
* xxd : 2022-01-14
|
2023-10-21 17:38:35 +00:00
|
|
|
* POSIX coreutils : GNU coreutils 9.4
|
2023-02-10 13:27:15 +00:00
|
|
|
|
2023-03-05 06:37:07 +00:00
|
|
|
After that you can run `make` on the top level directory and it should build everything and start the simulation
|
2023-02-13 16:49:17 +00:00
|
|
|
|
2023-03-21 12:38:35 +00:00
|
|
|
### High level design overview
|
2023-05-16 13:06:01 +00:00
|
|
|
|
2023-03-21 12:38:35 +00:00
|
|
|
<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
|
|
|
|
|
|
2023-02-13 16:49:17 +00:00
|
|
|
### License
|
2023-11-02 00:23:35 +00:00
|
|
|
All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later
|
|
|
|
|
|
|
|
|
|
Efthymios Kritikos is the copyright owner for all files except the following:
|
|
|
|
|
|
|
|
|
|
| File | Copyright owner | Original license |
|
|
|
|
|
| :-----------------------------------------------------: | :-------------: | :--------------: |
|
|
|
|
|
| system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf | Greg Davill | MIT |
|
2023-05-04 02:21:53 +00:00
|
|
|
|
2023-05-04 02:47:25 +00:00
|
|
|
### Version names
|
|
|
|
|
The version name consist of three numbers:
|
2023-05-04 02:21:53 +00:00
|
|
|
|
|
|
|
|
1. The CPU that this version aims to be compatible with
|
|
|
|
|
1. The specific milestone
|
|
|
|
|
1. Patch level
|
|
|
|
|
|
|
|
|
|
For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached.
|
