9086/system/fpga_config/OrangeCrab_r0.2.1/verilator_config.vlt

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`verilator_config
lint_off -rule COMBDLY -file "external_ip/litedram_core_ecp5_phy_sim.v"
lint_off -rule CASEINCOMPLETE -file "external_ip/litedram_core_ecp5_phy_sim.v"
lint_off -rule UNUSEDSIGNAL -file "external_ip/litedram_core_ecp5_phy_sim.v"
lint_off -rule WIDTHEXPAND -file "external_ip/litedram_core_ecp5_phy_sim.v"
lint_off -rule WIDTHTRUNC -file "external_ip/litedram_core_ecp5_phy_sim.v"