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<img width="140" height="52" align="left" style="float: left; margin: 0 10px 0 0;" alt="9086 logo" src="https://git.efthimiskritikos.com/Efthimis/Testing/raw/branch/master/9086.svg"> <img width="186" height="70" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_design1.svg">
# 9086
### Most instructions follow this format A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.
| 6bit | 1bit | 1bit | 2bit | 3bit | 3bit |
| ----- | --------- | ---- | --------------- | ------------ | ---- |
| OpCod | Direction | Size | Addressing mode | Register ID | Specific addressign mode|
| Register ID | Register Name| ### Progress
|:-------------:|:-------------:|
|0 0 0 |AL AX|
|0 0 1 |CL CX|
|0 1 0 |DL DX|
|0 1 1 |BL BX|
|1 0 0 |AH SP|
|1 0 1 |CH BP|
|1 1 0 |DH SI|
|1 1 1 |BH DI|
* [ ] Not checked * [ ] 8086
* [ ] still checked * [X] Executing code
* [almost] checked * [X] Is Turing complete
* [x] checked * [ ] Can boot up MS-DOS / FreeDOS
* [ ] Is completely binary compatible
* [X] Is pipelined
* [ ] Is Out of Order
* [ ] Is superscalar
* [ ] Has been successfully synthesized
|.. |.. |.. |.. | O | D | I | T | S | Z |.. | A |.. | P |.. | C | ### Simulating it
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk)
Specifically this list shows the software needed and the versions used during development (other versions should work as well)
* Icarus Verilog : version 12.0 OR **(preferred)** Verilator : 5.016
* bin86 : 0.16.21
* GNU Make : 4.4.1
* xxd : 2022-01-14
* POSIX coreutils : GNU coreutils 9.4
After that you can run `make` on the top level directory and it should build everything and start the simulation
### High level design overview
<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
### License
All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later
Efthymios Kritikos is the copyright owner for all files except the following:
| ------------------------------------------------------- | ----------- |
| system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf | Greg Davill |
### Version names
The version name consist of three numbers:
1. The CPU that this version aims to be compatible with
1. The specific milestone
1. Patch level
For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached.