From c2d6e5d964c02adc6a1ac45bc8446ae6a5ebe30c Mon Sep 17 00:00:00 2001 From: "(Tim) Efthimis Kritikos" Date: Thu, 4 May 2023 03:18:59 +0100 Subject: [PATCH] Test new readme --- README.md | 44 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 21bb7b0..4dbc45b 100644 --- a/README.md +++ b/README.md @@ -1,3 +1,43 @@ -### Project name test +9086 logo -Heading test + +A CPU that aims to be binary compatible with the 8086 and with as many optimisations as possible + +### Progress + +* [X] 8086 + * [X] Executing code + * [X] Is Turing complete + * [ ] Can boot up MS-DOS / FreeDOS + * [ ] Is completely binary compatible + * [ ] Is pipelined + * [ ] Is Out of Order + * [ ] Is superscalar + * [ ] Has been successfully synthesized + +### Simulating it +Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk) +Specifically this list shows the software needed and the versions used during development (other versions should work as well) + +* Icarus Verilog : version 11.0 OR **(preferred)** Verilator : 5.006 +* bin86 : 0.16.21 +* GNU Make : 4.4.1 +* xxd : 2022-01-14 +* POSIX coreutils : GNU coreutils 9.1 + +After that you can run `make` on the top level directory and it should build everything and start the simulation + +### High level design overview +9086 logo + +### License +All parts of this project are licensed under the GNU General Public License version 3 or later + +### Versions +The version consist of three numbers: + +1. The CPU that this version aims to be compatible with +1. The specific milestone +1. Patch level + +For example v1.3.2 aims to support 80186 code, is on the third milestone and has 2 bug fixes since the milestone was reached.