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-### Project name test
+<img width="186" height="70" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_design1.svg">
 
-Heading test
+
+A CPU that aims to be binary compatible with the 8086 and with as many optimisations as possible
+
+### Progress
+
+* [X] 8086
+  * [X] Executing code
+  * [X] Is Turing complete
+  * [ ] Can boot up MS-DOS / FreeDOS
+  * [ ] Is completely binary compatible
+  * [ ] Is pipelined
+  * [ ] Is Out of Order
+  * [ ] Is superscalar
+  * [ ] Has been successfully synthesized
+
+### Simulating it
+Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk)
+Specifically this list shows the software needed and the versions used during development (other versions should work as well)
+
+* Icarus Verilog : version 11.0  OR **(preferred)** Verilator : 5.006
+* bin86 : 0.16.21
+* GNU Make : 4.4.1
+* xxd : 2022-01-14
+* POSIX coreutils : GNU coreutils 9.1
+
+After that you can run `make` on the top level directory and it should build everything and start the simulation
+
+### High level design overview
+<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
+
+### License
+All parts of this project are licensed under the GNU General Public License version 3 or later
+
+### Versions
+The version consist of three numbers:
+
+1. The CPU that this version aims to be compatible with
+1. The specific milestone
+1. Patch level
+
+For example v1.3.2 aims to support 80186 code, is on the third milestone and has 2 bug fixes since the milestone was reached.