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(Tim) Efthimis Kritikos 2023-11-07 13:24:51 +00:00
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@ -13,7 +13,11 @@ A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisati
* [X] Is pipelined * [X] Is pipelined
* [ ] Is Out of Order * [ ] Is Out of Order
* [ ] Is superscalar * [ ] Is superscalar
* [ ] Has been successfully synthesized * [X] Has been successfully synthesized
### High level design overview
<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
### Simulating it ### Simulating it
Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk) Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk)
@ -27,18 +31,34 @@ Specifically this list shows the software needed and the versions used during de
After that you can run `make` on the top level directory and it should build everything and start the simulation After that you can run `make` on the top level directory and it should build everything and start the simulation
### High level design overview ### Synthesis and bitstream creation ( for FPGAs )
Synthesis is based on yosys. You need to select your board in [common.mk](./common.mk) which is basically a directory inside [system/fpga\_config/](system/fpga_config/) which had configuration files specifically for that board. You should also check inside your board directory for config.mk for further configuration options specific to the board. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg"> This list shows the software needed and the versions used during development
* yosys : 0.35
* bin86 : 0.16.21
* GNU Make : 4.4.1
* xxd : 2022-01-14
* POSIX coreutils : GNU coreutils 9.4
For ECP5 FPGAs:
* prjtrellis : 1.4 ( database commit 4dda149b9e4f1753ebc8b011ece2fe794be1281a )
* nextpnr : 0.6
For FPGAs using the [foboot](https://github.com/im-tomu/foboot) bootloader
* dfu-util : 0.11
### License ### License
All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later
Efthymios Kritikos is the copyright owner for all files except the following: Efthymios Kritikos is the copyright owner for all files except the following:
| File | Copyright owner | Original license | | File | Copyright owner | Original license |
| :-----------------------------------------------------: | :-------------: | :--------------: | | :--------------------------------------------------------: | :-------------: | :--------------: |
| system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf | Greg Davill | MIT | | system/fpga\_config/OrangeCrab\_r0.2.1/pin\_constraint.pcf | Greg Davill | MIT |
### Version names ### Version names
The version name consist of three numbers: The version name consist of three numbers: