From 80a323118bf7db6a94792ae31cfaf3363825d0e0 Mon Sep 17 00:00:00 2001
From: "(Tim) Efthimis Kritikos" <efkf@firemail.cc>
Date: Tue, 7 Nov 2023 13:50:18 +0000
Subject: [PATCH] edits

---
 test.md | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/test.md b/test.md
index 22f7d73..f9f09ed 100644
--- a/test.md
+++ b/test.md
@@ -20,8 +20,9 @@ A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisati
 <img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
 
 ### Simulating it
-Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [./common.mk](./common.mk)
-Specifically this list shows the software needed and the versions used during development (other versions should work as well)
+Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [./common.mk](./common.mk).
+
+This list shows the software needed and the versions used during development
 
 * Icarus Verilog : version 12.0  OR **(preferred)** Verilator : 5.016
 * bin86 : 0.16.21