2023-11-01 23:58:30 +00:00
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<img width="186" height="70" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_design1.svg">
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A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.
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### Progress
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* [ ] 8086
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* [X] Executing code
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* [X] Is Turing complete
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* [ ] Can boot up MS-DOS / FreeDOS
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* [ ] Is completely binary compatible
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* [X] Is pipelined
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* [ ] Is Out of Order
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* [ ] Is superscalar
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* [ ] Has been successfully synthesized
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### Simulating it
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Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk)
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Specifically this list shows the software needed and the versions used during development (other versions should work as well)
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* Icarus Verilog : version 12.0 OR **(preferred)** Verilator : 5.016
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* bin86 : 0.16.21
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* GNU Make : 4.4.1
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* xxd : 2022-01-14
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* POSIX coreutils : GNU coreutils 9.4
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After that you can run `make` on the top level directory and it should build everything and start the simulation
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### High level design overview
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<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
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### License
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All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later
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Efthymios Kritikos is the copyright owner for all files except the following:
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2023-11-01 23:59:06 +00:00
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2023-11-01 23:58:30 +00:00
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| ------------------------------------------------------- | ----------- |
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| system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf | Greg Davill |
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### Version names
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The version name consist of three numbers:
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1. The CPU that this version aims to be compatible with
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1. The specific milestone
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1. Patch level
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For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached.
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