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base: Efthimis:d048b080b8295fdce0a6b71b9c3e23a12dc0a96b
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Efthimis:master
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compare: Efthimis:3e86db960016bb3ad934b3bc5984d4bbc62cd57a
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Efthimis:master

2 Commits
d048b080b8 ... 3e86db9600

Author SHA1 Message Date
(Tim) Efthimis Kritikos
3e86db9600 CPU: Fixed a bug with memory access on the RET instruction 2024-05-04 07:29:45 +01:00
(Tim) Efthimis Kritikos
39af6ec292 ASM: Fixed length checking bug in assembler labels 2024-05-03 14:06:56 +01:00
2 changed files with 2 additions and 2 deletions
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2
assembly.c
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@ -356,7 +356,7 @@ struct imm_ret_t *parse_immediate(char* str,struct assembler_context_t *assemble
struct label_ll_t *search=assembler_context->label_ll; struct label_ll_t *search=assembler_context->label_ll;
while(search){ while(search){
if(strncmp(str,search->name,len)==0){ if(strncmp(str,search->name,len)==0&&search->name[len]==0){
if(select==1) if(select==1)
imm_ret->value=search->address>>16; imm_ret->value=search->address>>16;
else if(select==2) else if(select==2)

2
cpu.c
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@ -384,7 +384,7 @@ int exec(struct simdata_t *simdata){
case RET: case RET:
simdata->exec_data->cycles_left=delay_values[CALL_RET_INDX]; simdata->exec_data->cycles_left=delay_values[CALL_RET_INDX];
simdata->registers->SP-=4; simdata->registers->SP-=4;
simdata->registers->PC=simdata->RAM[simdata->registers->SP]; simdata->registers->PC=*(uint32_t*)(simdata->RAM+simdata->registers->SP);
break; break;
case EXEC_ALU: case EXEC_ALU:
if( simdata->exec_data->in_op1->OP_ADDR==REGISTER && if( simdata->exec_data->in_op1->OP_ADDR==REGISTER &&