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base: Efthimis:8f817a17b77ac2ed8ff9309bcc187c3ea3db3c68
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Efthimis:master
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compare: Efthimis:a03111927221ef3bffb88073331644f0d22d13d1
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Efthimis:master

2 Commits
8f817a17b7 ... a031119272

Author SHA1 Message Date
(Tim) Efthimis Kritikos
a031119272 CPU,ASM: Added register to register MOV instruction 2024-02-17 19:52:27 +00:00
(Tim) Efthimis Kritikos
5d4916339d CPU,ASM: Added the INC/DEC instructions 2024-02-17 19:30:39 +00:00
3 changed files with 60 additions and 1 deletions
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35
assembly.c
View File

@ -116,6 +116,12 @@
// | 14'hE | Calculate the sin of a register | YES | operand | |
// +-------+---------------------------------------------+--------------+------------+------------+
// | 14'hF | Calculate the cos of a register | YES | operand | |
// +-------+---------------------------------------------+--------------+------------+------------+
// | 14'h10| DEC | YES | operand | |
// +-------+---------------------------------------------+--------------+------------+------------+
// | 14'h11| INC | YES | operand | |
// +-------+---------------------------------------------+--------------+------------+------------+
// | 14'h12| MOV | YES | operand | |
//
//
// INSTRUCTION FORMAT 2 OPCODE NUM:
@ -233,6 +239,15 @@ char *disassemble(uint32_t opcode_be){
case 0x0F:
snprintf(ret,MAX_INSTRUCTION_LENGTH,"COS %%R%0d",val1);
break;
case 0x10:
snprintf(ret,MAX_INSTRUCTION_LENGTH,"DEC %%R%0d",val1);
break;
case 0x11:
snprintf(ret,MAX_INSTRUCTION_LENGTH,"INC %%R%0d",val1);
break;
case 0x12:
snprintf(ret,MAX_INSTRUCTION_LENGTH,"MOV %%R%0d,%%R%0d",val1,val2);
break;
default:
snprintf(ret,MAX_INSTRUCTION_LENGTH,"UNRECOGNISED INSTRUCTION");
break;
@ -449,6 +464,14 @@ int64_t assemble_line(char *line, struct assembler_context_t *assembler_context)
x=3;
opcode=0x200F;
params=1;
}else if(strncmp(line,"DEC ",4)==0){
x=3;
opcode=0x2010;
params=1;
}else if(strncmp(line,"INC ",4)==0){
x=3;
opcode=0x2011;
params=1;
}else
params=0;
if(params!=0){
@ -578,6 +601,18 @@ int64_t assemble_line(char *line, struct assembler_context_t *assembler_context)
return -2;
}else
return -2;
}else if(line[x]=='%'){
x++;
if(line[x]=='R'){
x++;
if(line[x]>='0'&&line[x]<='7'){
r1=line[x]-'0';
return 0x20120000|(r0&0xFF)<<8|(r1&0xFF);
}else
return -2;
}else
return -2;
}else
return -2;
}else

22
cpu.c
View File

@ -97,6 +97,9 @@ int decode(struct simdata_t *simdata){
case 0x0D:
case 0x0E:
case 0x0F:
case 0x10:
case 0x11:
case 0x12:
simdata->exec_data->in_op1->OP_ADDR=REGISTER;
simdata->exec_data->in_op2->OP_ADDR=REGISTER;
break;
@ -122,6 +125,7 @@ int decode(struct simdata_t *simdata){
break;
case 0x08:
case 0x09:
case 0x12:
simdata->exec_data->EXEC_ACTION=MOVE;
break;
default:
@ -137,6 +141,7 @@ int decode(struct simdata_t *simdata){
case 0x0B:
case 0x0C:
case 0x0D:
case 0x12:
simdata->exec_data->out_op->OP_ADDR=REGISTER;
simdata->exec_data->out_op->data=op2;
break;
@ -144,6 +149,8 @@ int decode(struct simdata_t *simdata){
case 0x03:
case 0x0E:
case 0x0F:
case 0x10:
case 0x11:
simdata->exec_data->out_op->OP_ADDR=REGISTER;
simdata->exec_data->out_op->data=op1;
break;
@ -169,6 +176,7 @@ int decode(struct simdata_t *simdata){
case 0x07:
case 0x08:
case 0x09:
case 0x12:
break;
case 0x0A: simdata->exec_data->ALU_OP=ALU_FDIV; break;
case 0x0B: simdata->exec_data->ALU_OP=ALU_FMUL; break;
@ -176,6 +184,8 @@ int decode(struct simdata_t *simdata){
case 0x0D: simdata->exec_data->ALU_OP=ALU_FSUB; break;
case 0x0E: simdata->exec_data->ALU_OP=ALU_FSIN; break;
case 0x0F: simdata->exec_data->ALU_OP=ALU_FCOS; break;
case 0x10: simdata->exec_data->ALU_OP=ALU_DEC; break;
case 0x11: simdata->exec_data->ALU_OP=ALU_INC; break;
default:
return 1;
}
@ -325,6 +335,16 @@ int exec(struct simdata_t *simdata){
case ALU_FCOS:
*(float*)&result = cosf(*(float*)(&simdata->registers->GPR[simdata->exec_data->in_op1->data]));
break;
case ALU_DEC:
*(uint32_t*)&result = *(uint32_t*)(&simdata->registers->GPR[simdata->exec_data->in_op1->data])-1;
simdata->registers->FLAGS=(simdata->registers->FLAGS&0xFFFFFFFD)|
(simdata->registers->GPR[simdata->exec_data->out_op->data] > simdata->registers->GPR[simdata->exec_data->in_op1->data])<<1;
break;
case ALU_INC:
*(uint32_t*)&result = *(uint32_t*)(&simdata->registers->GPR[simdata->exec_data->in_op1->data])+1;
simdata->registers->FLAGS=(simdata->registers->FLAGS&0xFFFFFFFD)|
(simdata->registers->GPR[simdata->exec_data->out_op->data] > simdata->registers->GPR[simdata->exec_data->in_op1->data])<<1;
break;
default:
return 1;
}
@ -370,6 +390,8 @@ int exec(struct simdata_t *simdata){
simdata->registers->GPR[simdata->exec_data->out_op->data]=*(uint32_t*)(simdata->RAM+simdata->registers->GPR[simdata->exec_data->in_op1->data]);
else
return 2;
}else if(simdata->exec_data->in_op1->OP_ADDR==REGISTER){
simdata->registers->GPR[simdata->exec_data->out_op->data]=simdata->registers->GPR[simdata->exec_data->in_op1->data];
}else
return 1;
break;

4
cpu.h
View File

@ -36,7 +36,9 @@ enum ALU_OP_t {
ALU_FADD,
ALU_FSUB,
ALU_FSIN,
ALU_FCOS
ALU_FCOS,
ALU_DEC,
ALU_INC
};
enum OP_ADDR_t {