Efthimis/First
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Compare commits

base: Efthimis:3e86db960016bb3ad934b3bc5984d4bbc62cd57a
Branches Tags
Efthimis:master
..
compare: Efthimis:d048b080b8295fdce0a6b71b9c3e23a12dc0a96b
Branches Tags
Efthimis:master

No commits in common. "3e86db960016bb3ad934b3bc5984d4bbc62cd57a" and "d048b080b8295fdce0a6b71b9c3e23a12dc0a96b" have entirely different histories.
3e86db9600 ... d048b080b8

2 changed files with 2 additions and 2 deletions
Show Stats Expand all files Collapse all files

2
assembly.c
View File

@ -356,7 +356,7 @@ struct imm_ret_t *parse_immediate(char* str,struct assembler_context_t *assemble
struct label_ll_t *search=assembler_context->label_ll; struct label_ll_t *search=assembler_context->label_ll;
while(search){ while(search){
if(strncmp(str,search->name,len)==0&&search->name[len]==0){ if(strncmp(str,search->name,len)==0){
if(select==1) if(select==1)
imm_ret->value=search->address>>16; imm_ret->value=search->address>>16;
else if(select==2) else if(select==2)

2
cpu.c
View File

@ -384,7 +384,7 @@ int exec(struct simdata_t *simdata){
case RET: case RET:
simdata->exec_data->cycles_left=delay_values[CALL_RET_INDX]; simdata->exec_data->cycles_left=delay_values[CALL_RET_INDX];
simdata->registers->SP-=4; simdata->registers->SP-=4;
simdata->registers->PC=*(uint32_t*)(simdata->RAM+simdata->registers->SP); simdata->registers->PC=simdata->RAM[simdata->registers->SP];
break; break;
case EXEC_ALU: case EXEC_ALU:
if( simdata->exec_data->in_op1->OP_ADDR==REGISTER && if( simdata->exec_data->in_op1->OP_ADDR==REGISTER &&