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CPU,ASM: Added register to register MOV instruction

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(Tim) Efthimis Kritikos 2024-02-17 19:52:27 +00:00
parent 5d4916339d
commit a031119272
2 changed files with 23 additions and 0 deletions
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17
assembly.c
View File

@ -120,6 +120,8 @@
// | 14'h10| DEC | YES | operand | |
// +-------+---------------------------------------------+--------------+------------+------------+
// | 14'h11| INC | YES | operand | |
// +-------+---------------------------------------------+--------------+------------+------------+
// | 14'h12| MOV | YES | operand | |
//
//
// INSTRUCTION FORMAT 2 OPCODE NUM:
@ -243,6 +245,9 @@ char *disassemble(uint32_t opcode_be){
case 0x11:
snprintf(ret,MAX_INSTRUCTION_LENGTH,"INC %%R%0d",val1);
break;
case 0x12:
snprintf(ret,MAX_INSTRUCTION_LENGTH,"MOV %%R%0d,%%R%0d",val1,val2);
break;
default:
snprintf(ret,MAX_INSTRUCTION_LENGTH,"UNRECOGNISED INSTRUCTION");
break;
@ -596,6 +601,18 @@ int64_t assemble_line(char *line, struct assembler_context_t *assembler_context)
return -2;
}else
return -2;
}else if(line[x]=='%'){
x++;
if(line[x]=='R'){
x++;
if(line[x]>='0'&&line[x]<='7'){
r1=line[x]-'0';
return 0x20120000|(r0&0xFF)<<8|(r1&0xFF);
}else
return -2;
}else
return -2;
}else
return -2;
}else

6
cpu.c
View File

@ -99,6 +99,7 @@ int decode(struct simdata_t *simdata){
case 0x0F:
case 0x10:
case 0x11:
case 0x12:
simdata->exec_data->in_op1->OP_ADDR=REGISTER;
simdata->exec_data->in_op2->OP_ADDR=REGISTER;
break;
@ -124,6 +125,7 @@ int decode(struct simdata_t *simdata){
break;
case 0x08:
case 0x09:
case 0x12:
simdata->exec_data->EXEC_ACTION=MOVE;
break;
default:
@ -139,6 +141,7 @@ int decode(struct simdata_t *simdata){
case 0x0B:
case 0x0C:
case 0x0D:
case 0x12:
simdata->exec_data->out_op->OP_ADDR=REGISTER;
simdata->exec_data->out_op->data=op2;
break;
@ -173,6 +176,7 @@ int decode(struct simdata_t *simdata){
case 0x07:
case 0x08:
case 0x09:
case 0x12:
break;
case 0x0A: simdata->exec_data->ALU_OP=ALU_FDIV; break;
case 0x0B: simdata->exec_data->ALU_OP=ALU_FMUL; break;
@ -386,6 +390,8 @@ int exec(struct simdata_t *simdata){
simdata->registers->GPR[simdata->exec_data->out_op->data]=*(uint32_t*)(simdata->RAM+simdata->registers->GPR[simdata->exec_data->in_op1->data]);
else
return 2;
}else if(simdata->exec_data->in_op1->OP_ADDR==REGISTER){
simdata->registers->GPR[simdata->exec_data->out_op->data]=simdata->registers->GPR[simdata->exec_data->in_op1->data];
}else
return 1;
break;