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CPU,ASM: Added the INC/DEC instructions

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(Tim) Efthimis Kritikos 2024-02-17 19:30:39 +00:00
parent 8f817a17b7
commit 5d4916339d
3 changed files with 37 additions and 1 deletions
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18
assembly.c
View File

@ -116,6 +116,10 @@
// | 14'hE | Calculate the sin of a register | YES | operand | | // | 14'hE | Calculate the sin of a register | YES | operand | |
// +-------+---------------------------------------------+--------------+------------+------------+ // +-------+---------------------------------------------+--------------+------------+------------+
// | 14'hF | Calculate the cos of a register | YES | operand | | // | 14'hF | Calculate the cos of a register | YES | operand | |
// +-------+---------------------------------------------+--------------+------------+------------+
// | 14'h10| DEC | YES | operand | |
// +-------+---------------------------------------------+--------------+------------+------------+
// | 14'h11| INC | YES | operand | |
// //
// //
// INSTRUCTION FORMAT 2 OPCODE NUM: // INSTRUCTION FORMAT 2 OPCODE NUM:
@ -233,6 +237,12 @@ char *disassemble(uint32_t opcode_be){
case 0x0F: case 0x0F:
snprintf(ret,MAX_INSTRUCTION_LENGTH,"COS %%R%0d",val1); snprintf(ret,MAX_INSTRUCTION_LENGTH,"COS %%R%0d",val1);
break; break;
case 0x10:
snprintf(ret,MAX_INSTRUCTION_LENGTH,"DEC %%R%0d",val1);
break;
case 0x11:
snprintf(ret,MAX_INSTRUCTION_LENGTH,"INC %%R%0d",val1);
break;
default: default:
snprintf(ret,MAX_INSTRUCTION_LENGTH,"UNRECOGNISED INSTRUCTION"); snprintf(ret,MAX_INSTRUCTION_LENGTH,"UNRECOGNISED INSTRUCTION");
break; break;
@ -449,6 +459,14 @@ int64_t assemble_line(char *line, struct assembler_context_t *assembler_context)
x=3; x=3;
opcode=0x200F; opcode=0x200F;
params=1; params=1;
}else if(strncmp(line,"DEC ",4)==0){
x=3;
opcode=0x2010;
params=1;
}else if(strncmp(line,"INC ",4)==0){
x=3;
opcode=0x2011;
params=1;
}else }else
params=0; params=0;
if(params!=0){ if(params!=0){

16
cpu.c
View File

@ -97,6 +97,8 @@ int decode(struct simdata_t *simdata){
case 0x0D: case 0x0D:
case 0x0E: case 0x0E:
case 0x0F: case 0x0F:
case 0x10:
case 0x11:
simdata->exec_data->in_op1->OP_ADDR=REGISTER; simdata->exec_data->in_op1->OP_ADDR=REGISTER;
simdata->exec_data->in_op2->OP_ADDR=REGISTER; simdata->exec_data->in_op2->OP_ADDR=REGISTER;
break; break;
@ -144,6 +146,8 @@ int decode(struct simdata_t *simdata){
case 0x03: case 0x03:
case 0x0E: case 0x0E:
case 0x0F: case 0x0F:
case 0x10:
case 0x11:
simdata->exec_data->out_op->OP_ADDR=REGISTER; simdata->exec_data->out_op->OP_ADDR=REGISTER;
simdata->exec_data->out_op->data=op1; simdata->exec_data->out_op->data=op1;
break; break;
@ -176,6 +180,8 @@ int decode(struct simdata_t *simdata){
case 0x0D: simdata->exec_data->ALU_OP=ALU_FSUB; break; case 0x0D: simdata->exec_data->ALU_OP=ALU_FSUB; break;
case 0x0E: simdata->exec_data->ALU_OP=ALU_FSIN; break; case 0x0E: simdata->exec_data->ALU_OP=ALU_FSIN; break;
case 0x0F: simdata->exec_data->ALU_OP=ALU_FCOS; break; case 0x0F: simdata->exec_data->ALU_OP=ALU_FCOS; break;
case 0x10: simdata->exec_data->ALU_OP=ALU_DEC; break;
case 0x11: simdata->exec_data->ALU_OP=ALU_INC; break;
default: default:
return 1; return 1;
} }
@ -325,6 +331,16 @@ int exec(struct simdata_t *simdata){
case ALU_FCOS: case ALU_FCOS:
*(float*)&result = cosf(*(float*)(&simdata->registers->GPR[simdata->exec_data->in_op1->data])); *(float*)&result = cosf(*(float*)(&simdata->registers->GPR[simdata->exec_data->in_op1->data]));
break; break;
case ALU_DEC:
*(uint32_t*)&result = *(uint32_t*)(&simdata->registers->GPR[simdata->exec_data->in_op1->data])-1;
simdata->registers->FLAGS=(simdata->registers->FLAGS&0xFFFFFFFD)|
(simdata->registers->GPR[simdata->exec_data->out_op->data] > simdata->registers->GPR[simdata->exec_data->in_op1->data])<<1;
break;
case ALU_INC:
*(uint32_t*)&result = *(uint32_t*)(&simdata->registers->GPR[simdata->exec_data->in_op1->data])+1;
simdata->registers->FLAGS=(simdata->registers->FLAGS&0xFFFFFFFD)|
(simdata->registers->GPR[simdata->exec_data->out_op->data] > simdata->registers->GPR[simdata->exec_data->in_op1->data])<<1;
break;
default: default:
return 1; return 1;
} }

4
cpu.h
View File

@ -36,7 +36,9 @@ enum ALU_OP_t {
ALU_FADD, ALU_FADD,
ALU_FSUB, ALU_FSUB,
ALU_FSIN, ALU_FSIN,
ALU_FCOS ALU_FCOS,
ALU_DEC,
ALU_INC
}; };
enum OP_ADDR_t { enum OP_ADDR_t {