CPU,ASM: Added support for writing to register indirect locations and mapper the temrinal into the address space

assembly.c

@@ -81,26 +81,29 @@
 //  |       |                                  |              |
 //
 //
-//
 //  INSTRUCTION FORMAT 1 OPCODE NUM:
-//  +-------+----------------------------------+--------------+------------+------------+
+//  +-------+---------------------------------------------+--------------+------------+------------+
 //  | NUM   | DESCRIPTION                                 | AFFECT FLAGS | SOURCE REG |  DEST REG  |
-//  +-------+----------------------------------+--------------+------------+------------+
+//  +-------+---------------------------------------------+--------------+------------+------------+
-//  | 13'd0 | ADD                              |      YES     |  operand 1 |  operand 1 |
+//  | 13'h0 | ADD                                         |      YES     |  operand 1 |  operand 1 |
-//  +-------+----------------------------------+--------------|------------+------------+
+//  +-------+---------------------------------------------+--------------|------------+------------+
-//  | 13'd1 | SUBTRACT                         |      YES     |  operand 1 |  operand 1 |
+//  | 13'h1 | SUBTRACT                                    |      YES     |  operand 1 |  operand 1 |
-//  +-------+----------------------------------+--------------|------------+------------+
+//  +-------+---------------------------------------------+--------------|------------+------------+
-//  | 13'd2 | SHIFT LEFT                       |      YES     |   operand  |            |
+//  | 13'h2 | SHIFT LEFT                                  |      YES     |   operand  |            |
-//  +-------+----------------------------------+--------------|------------+------------+
+//  +-------+---------------------------------------------+--------------|------------+------------+
-//  | 13'd3 | SHIFT RIGHT                      |      YES     |   operand  |            |
+//  | 13'h3 | SHIFT RIGHT                                 |      YES     |   operand  |            |
-//  +-------+----------------------------------+--------------|------------+------------+
+//  +-------+---------------------------------------------+--------------|------------+------------+
-//  | 13'd4 | COMPARE  (SUBTRACT WITHOUT SAVE) |      YES     |  operand 1 |  operand 1 |
+//  | 13'h4 | COMPARE  (SUBTRACT WITHOUT SAVE)            |      YES     |  operand 1 |  operand 1 |
-//  +-------+----------------------------------+--------------+------------+------------+
+//  +-------+---------------------------------------------+--------------+------------+------------+
-//  | 13'd5 | HALT                             |      NO      |            |            |
+//  | 13'h5 | HALT                                        |      NO      |            |            |
-//  +-------+----------------------------------+--------------+------------+------------+
+//  +-------+---------------------------------------------+--------------+------------+------------+
-//  | 13'd6 | PUSH                             |      NO      |   operand  |            |
+//  | 13'h6 | PUSH                                        |      NO      |   operand  |            |
-//  +-------+----------------------------------+--------------+------------+------------+
+//  +-------+---------------------------------------------+--------------+------------+------------+
-//  | 13'd7 | POP                              |      NO      |   operand  |            |
+//  | 13'h7 | POP                                         |      NO      |   operand  |            |
+//  +-------+---------------------------------------------+--------------+------------+------------+
+//  | 13'h8 | MOV register to indirect register ( 32-bit )|      NO      |   operand  | (operand)  |
+//  +-------+---------------------------------------------+--------------+------------+------------+
+//  | 13'h9 | MOV indirect register to register ( 32-bit )|      NO      |  (operand) |  operand   |
 //
 //
 //  INSTRUCTION FORMAT 2 OPCODE NUM:
@@ -194,6 +197,12 @@ char *disassemble(uint32_t opcode_be){
 			case 0x07:
 				snprintf(ret,MAX_INSTRUCTION_LENGTH,"POP %%R%0d",val1);
 				break;
+			case 0x08:
+				snprintf(ret,MAX_INSTRUCTION_LENGTH,"MOV %%R%0d,(%%R%0d)",val1,val2);
+				break;
+			case 0x09:
+				snprintf(ret,MAX_INSTRUCTION_LENGTH,"MOV (%%R%0d),%%R%0d",val1,val2);
+				break;
 			default:
 				snprintf(ret,MAX_INSTRUCTION_LENGTH,"UNRECOGNISED INSTRUCTION");
 				break;
@@ -407,6 +416,46 @@ uint32_t assemble_line(char *line, struct assembler_context_t *assembler_context
 						return 0xFFFFFFFF;
 				}else
 					return 0xFFFFFFFF;
+			}else if(line[x]=='%'){
+				x++;
+				if(line[x]=='R'){
+					x++;
+					if(line[x]>='0'&&line[x]<='7'){
+						r0=line[x]-'0';
+						x++;
+						while(line[x]==' ')x++;
+						if(line[x]==','){
+							x++;
+							while(line[x]==' ')x++;
+							if(line[x]=='('){
+								x++;
+								while(line[x]==' ')x++;
+								if(line[x]=='%'){
+									x++;
+									if(line[x]=='R'){
+										x++;
+										if(line[x]>='0'&&line[x]<='7'){
+											r1=line[x]-'0';
+											x++;
+											while(line[x]==' ')x++;
+											if(line[x]==')'){
+												return 0x20080000|(r0&0xFF)<<8|(r1&0xFF);
+											}else
+												return 0xFFFFFFFF;
+										}else
+											return 0xFFFFFFFF;
+									}else
+										return 0xFFFFFFFF;
+								}else
+									return 0xFFFFFFFF;
+							}else
+								return 0xFFFFFFFF;
+						}else
+							return 0xFFFFFFFF;
+					}else
+						return 0xFFFFFFFF;
+				}else
+					return 0xFFFFFFFF;
 			}else
 				return 0xFFFFFFFF;
 		}else if(strncmp(line,"HALT",4)==0){

cpu.c

@@ -79,11 +79,28 @@ int decode(struct simdata_t *simdata){
 			op2=(simdata->decode_data->in_bytecode&0x000000FF);
 
 
-			simdata->exec_data->in_op1->OP_ADDR=REGISTER;
 			simdata->exec_data->in_op1->data=op1;
-
-			simdata->exec_data->in_op2->OP_ADDR=REGISTER;
 			simdata->exec_data->in_op2->data=op2;
+			switch(opcode){
+				case 0x01:
+				case 0x02:
+				case 0x03:
+				case 0x04:
+				case 0x05:
+				case 0x06:
+				case 0x07:
+					simdata->exec_data->in_op1->OP_ADDR=REGISTER;
+					simdata->exec_data->in_op2->OP_ADDR=REGISTER;
+					break;
+				case 0x08:
+					simdata->exec_data->in_op1->OP_ADDR=REGISTER;
+					simdata->exec_data->in_op2->OP_ADDR=REGISTER_IND;
+					break;
+				case 0x09:
+					simdata->exec_data->in_op1->OP_ADDR=REGISTER_IND;
+					simdata->exec_data->in_op2->OP_ADDR=REGISTER;
+					break;
+			}
 
 			switch(opcode){
 				case 0x05:
@@ -95,6 +112,10 @@ int decode(struct simdata_t *simdata){
 				case 0x07:
 					simdata->exec_data->EXEC_ACTION=POP;
 					break;
+				case 0x08:
+				case 0x09:
+					simdata->exec_data->EXEC_ACTION=MOVE;
+					break;
 				default:
 					simdata->exec_data->EXEC_ACTION=EXEC_ALU;
 					break;
@@ -112,6 +133,14 @@ int decode(struct simdata_t *simdata){
 					simdata->exec_data->out_op->OP_ADDR=REGISTER;
 					simdata->exec_data->out_op->data=op1;
 					break;
+				case 0x08:
+					simdata->exec_data->out_op->data=op2;
+					simdata->exec_data->out_op->OP_ADDR=REGISTER_IND;
+					break;
+				case 0x09:
+					simdata->exec_data->out_op->data=op2;
+					simdata->exec_data->out_op->OP_ADDR=REGISTER;
+					break;
 			}
 
 
@@ -121,9 +150,12 @@ int decode(struct simdata_t *simdata){
 				case 2: simdata->exec_data->ALU_OP=ALU_SL;  break;
 				case 3: simdata->exec_data->ALU_OP=ALU_SR;  break;
 				case 4: simdata->exec_data->ALU_OP=ALU_CMP;  break;
-				case 5: break;
+				case 5:
-				case 6: break;
+				case 6:
-				case 7: break;
+				case 7:
+				case 8:
+				case 9:
+					break;
 				default:
 					return 1;
 			}
@@ -291,6 +323,14 @@ int exec(struct simdata_t *simdata){
 							return 2;
 					}
 					break;
+				case REGISTER_IND:
+					if(simdata->exec_data->in_op1->OP_ADDR==REGISTER){
+						*(uint32_t*)(simdata->RAM+(simdata->registers->GPR[simdata->exec_data->out_op->data]&0x00FFFFFF))=simdata->registers->GPR[simdata->exec_data->in_op1->data];
+						if(simdata->registers->GPR[simdata->exec_data->out_op->data]==0x00FFFFFC)
+							terminal_output(simdata->registers->GPR[simdata->exec_data->in_op1->data],simdata);
+					}else
+						return 1;
+					break;
 				default:
 					return 1;
 			}

cpu.h

@@ -38,6 +38,7 @@ enum OP_ADDR_t {
 	REGISTER,
 	REGISTERL, //low word
 	REGISTERH, //high word
+	REGISTER_IND
 };
 
 struct exec_op_t {

test.asm

@@ -17,4 +17,17 @@ RET
 ADD %R0,%R1
 RET
 :END
-HALT
+MOV $0xFFFC,%R0l
+MOV $0x00FF,%R0h
+MOV $0x0068,%R1l
+MOV $0x0000,%R1h
+MOV %R1,(%R0)
+MOV $0x0065,%R1l
+MOV %R1,(%R0)
+MOV $0x006c,%R1l
+MOV %R1,(%R0)
+MOV $0x006c,%R1l
+MOV %R1,(%R0)
+MOV $0x006f,%R1l
+MOV %R1,(%R0)
+JMP $000000