CPU: Added support for reading into registers from indirect memory access with register
This commit is contained in:
parent
d643dc3e55
commit
35588a07c8
40
assembly.c
40
assembly.c
@ -456,6 +456,46 @@ int64_t assemble_line(char *line, struct assembler_context_t *assembler_context)
|
|||||||
return -2;
|
return -2;
|
||||||
}else
|
}else
|
||||||
return -2;
|
return -2;
|
||||||
|
}else if(line[x]=='('){
|
||||||
|
while(line[x]==' ')x++;
|
||||||
|
x++;
|
||||||
|
if(line[x]=='%'){
|
||||||
|
x++;
|
||||||
|
if(line[x]=='R'){
|
||||||
|
x++;
|
||||||
|
if(line[x]>='0'&&line[x]<='7'){
|
||||||
|
r0=line[x]-'0';
|
||||||
|
x++;
|
||||||
|
while(line[x]==' ')x++;
|
||||||
|
if(line[x]==')'){
|
||||||
|
x++;
|
||||||
|
while(line[x]==' ')x++;
|
||||||
|
if(line[x]==','){
|
||||||
|
x++;
|
||||||
|
while(line[x]==' ')x++;
|
||||||
|
if(line[x]=='%'){
|
||||||
|
x++;
|
||||||
|
if(line[x]=='R'){
|
||||||
|
x++;
|
||||||
|
if(line[x]>='0'&&line[x]<='7'){
|
||||||
|
r1=line[x]-'0';
|
||||||
|
return 0x20090000|(r0&0xFF)<<8|(r1&0xFF);
|
||||||
|
}else
|
||||||
|
return -2;
|
||||||
|
}else
|
||||||
|
return -2;
|
||||||
|
}else
|
||||||
|
return -2;
|
||||||
|
}else
|
||||||
|
return -2;
|
||||||
|
}else
|
||||||
|
return -2;
|
||||||
|
}else
|
||||||
|
return -2;
|
||||||
|
}else
|
||||||
|
return -2;
|
||||||
|
}else
|
||||||
|
return -2;
|
||||||
}else
|
}else
|
||||||
return -2;
|
return -2;
|
||||||
}else if(strncmp(line,"HALT ",5)==0||strncmp(line,"HALT\0",5)==0){
|
}else if(strncmp(line,"HALT ",5)==0||strncmp(line,"HALT\0",5)==0){
|
||||||
|
28
cpu.c
28
cpu.c
@ -59,12 +59,12 @@ int decode(struct simdata_t *simdata){
|
|||||||
simdata->exec_data->out_op->data=simdata->decode_data->in_bytecode&0x00FFFFFF;
|
simdata->exec_data->out_op->data=simdata->decode_data->in_bytecode&0x00FFFFFF;
|
||||||
simdata->exec_data->EXEC_ACTION=(opcode&0x10)?CALL:JUMP;
|
simdata->exec_data->EXEC_ACTION=(opcode&0x10)?CALL:JUMP;
|
||||||
break;
|
break;
|
||||||
case 0x0F:
|
case 0x0F:/* load SP */
|
||||||
simdata->exec_data->EXEC_ACTION=MOVE;
|
simdata->exec_data->EXEC_ACTION=MOVE;
|
||||||
simdata->exec_data->in_op1->OP_ADDR=IMMEDIATE;
|
simdata->exec_data->in_op1->OP_ADDR=IMMEDIATE;
|
||||||
simdata->exec_data->in_op1->data=simdata->decode_data->in_bytecode&0x00FFFFFF;
|
simdata->exec_data->in_op1->data=simdata->decode_data->in_bytecode&0x00FFFFFF;
|
||||||
simdata->exec_data->out_op->OP_ADDR=REGISTER;
|
simdata->exec_data->out_op->OP_ADDR=REGISTER;
|
||||||
simdata->exec_data->out_op->data=0;
|
simdata->exec_data->out_op->data=0xFF;
|
||||||
break;
|
break;
|
||||||
case 0x10:
|
case 0x10:
|
||||||
simdata->exec_data->EXEC_ACTION=RET;
|
simdata->exec_data->EXEC_ACTION=RET;
|
||||||
@ -311,17 +311,25 @@ int exec(struct simdata_t *simdata){
|
|||||||
simdata->registers->GPR[simdata->exec_data->in_op1->data])<<16);
|
simdata->registers->GPR[simdata->exec_data->in_op1->data])<<16);
|
||||||
break;
|
break;
|
||||||
case REGISTER: /* This is for special registers like the SP which is 24bits long */
|
case REGISTER: /* This is for special registers like the SP which is 24bits long */
|
||||||
if(simdata->exec_data->in_op1->OP_ADDR==IMMEDIATE){
|
if(simdata->exec_data->out_op->data==0xFF){
|
||||||
if( (simdata->exec_data->in_op1->data&0xFF000000) == 0 )
|
if(simdata->exec_data->in_op1->OP_ADDR==IMMEDIATE){
|
||||||
simdata->registers->SP=simdata->exec_data->in_op1->data;
|
if( (simdata->exec_data->in_op1->data&0xFF000000) == 0 )
|
||||||
else
|
simdata->registers->SP=simdata->exec_data->in_op1->data;
|
||||||
return 2;
|
else
|
||||||
}else{
|
return 2;
|
||||||
|
}else if( simdata->exec_data->in_op1->OP_ADDR==REGISTER ){ /*for completeion, not valid ( yet )*/
|
||||||
|
if( (simdata->registers->GPR[simdata->exec_data->in_op1->data]&0xFF000000) == 0 )
|
||||||
|
simdata->registers->SP=simdata->registers->GPR[simdata->exec_data->in_op1->data];
|
||||||
|
else
|
||||||
|
return 2;
|
||||||
|
}
|
||||||
|
}else if(simdata->exec_data->in_op1->OP_ADDR==REGISTER_IND){
|
||||||
if( (simdata->registers->GPR[simdata->exec_data->in_op1->data]&0xFF000000) == 0 )
|
if( (simdata->registers->GPR[simdata->exec_data->in_op1->data]&0xFF000000) == 0 )
|
||||||
simdata->registers->SP=simdata->registers->GPR[simdata->exec_data->in_op1->data];
|
simdata->registers->GPR[simdata->exec_data->out_op->data]=*(uint32_t*)(simdata->RAM+simdata->registers->GPR[simdata->exec_data->in_op1->data]);
|
||||||
else
|
else
|
||||||
return 2;
|
return 2;
|
||||||
}
|
}else
|
||||||
|
return 1;
|
||||||
break;
|
break;
|
||||||
case REGISTER_IND:
|
case REGISTER_IND:
|
||||||
if(simdata->exec_data->in_op1->OP_ADDR==REGISTER){
|
if(simdata->exec_data->in_op1->OP_ADDR==REGISTER){
|
||||||
|
Loading…
Reference in New Issue
Block a user