18 lines
289 B
Verilog
18 lines
289 B
Verilog
module counter(out, clk, reset);
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parameter WIDTH = 8;
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output [WIDTH: 0] out;
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input clk, reset;
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reg [WIDTH: 0] out;
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wire clk, reset;
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always @(posedge clk or posedge reset)
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if (reset)
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out <= 0;
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else
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out <= out + 1;
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endmodule // counter
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