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Efthimis
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COMS30046_2022_TB-2_playground
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Testing out mostly HDL and specifically verilog stuff
7
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49
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Verilog
52%
Coq
20.6%
C
14.9%
Makefile
12.5%
aeba97df05
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(Tim) Efthymios Kritikos
aeba97df05
Didn't add all files on last commit
2023-02-07 17:58:07 +00:00
verilog_iverilog
Didn't add all files on last commit
2023-02-07 17:58:07 +00:00
.gitignore
Added clock and gtkwave integration
2023-02-07 17:52:02 +00:00