module tb;
  wire clk1;
  wire clk2;
  wire clk3;
  wire clk4;
  reg  enable;
  reg [7:0] delay;
  
  clock_gen u0(enable, clk1);
  clock_gen #(.FREQ(100000)) u1(enable, clk2);
  clock_gen #(.FREQ(200000)) u2(enable, clk3);
  clock_gen #(.FREQ(400000)) u3(enable, clk4);
  integer i ;
  initial begin
	$dumpfile("test.lx2");
	    $dumpvars(0,u1,u2,u3);
    enable <= 0;
    
    for ( i = 0; i < 10; i=i+1) begin
      delay = $random;
      #(delay) enable <= ~enable;      
      $display("i=%0d delay=%0d", i, delay);
      #50;
    end
    
    #50 $finish;
  end
endmodule