module hello;
	wire out;
	reg A,B,X;
	multiplexer idk(A,B,X,out);
initial 
begin
	$display("RSLT\tOUT\tA\tB\tSLCT");
	A=1;B=1;X=1;#50
	if(out==1)
		$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
	else
		$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
	A=1;B=0;X=1;#50
	if(out==0)
		$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
	else
		$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
	A=0;B=1;X=1;#50
	if(out==1)
		$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
	else
		$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
	A=0;B=0;X=1;#50
	if(out==0)
		$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
	else
		$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
	A=1;B=1;X=0;#50
	if(out==1)
		$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
	else
		$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
	A=1;B=0;X=0;#50
	if(out==1)
		$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
	else
		$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
	A=0;B=1;X=0;#50
	if(out==0)
		$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
	else
		$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
	A=0;B=0;X=0;#50
	if(out==0)
		$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
	else
		$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
	$finish ;
end
endmodule