Dipping my toes into verilog development

verilog_iverilog/counter/Makefile

@@ -0,0 +1,5 @@
+counter: counter.vvp
+	vvp $<
+
+counter.vvp: counter.v counter_tb.v
+	iverilog $^ -o $@

verilog_iverilog/counter/counter.v

@@ -0,0 +1,17 @@
+module counter(out, clk, reset);
+
+  parameter WIDTH = 8;
+
+  output [WIDTH: 0] out;
+  input 	       clk, reset;
+
+  reg [WIDTH: 0]   out;
+  wire 	       clk, reset;
+
+  always @(posedge clk or posedge reset)
+    if (reset)
+      out <= 0;
+    else
+      out <= out + 1;
+
+endmodule // counter

verilog_iverilog/counter/counter.vvp

@@ -0,0 +1,86 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x55d800361b40 .scope module, "test" "test" 2 1;
+ .timescale 0 0;
+v0x55d800374740_0 .var "clk", 0 0;
+v0x55d800374810_0 .var "reset", 0 0;
+v0x55d8003748e0_0 .net "value", 7 0, L_0x55d8003749b0;  1 drivers
+L_0x55d8003749b0 .part v0x55d800374510_0, 0, 8;
+S_0x55d800361cd0 .scope module, "c1" "counter" 2 18, 3 1 0, S_0x55d800361b40;
+ .timescale 0 0;
+    .port_info 0 /OUTPUT 9 "out";
+    .port_info 1 /INPUT 1 "clk";
+    .port_info 2 /INPUT 1 "reset";
+P_0x55d800361eb0 .param/l "WIDTH" 0 3 3, +C4<00000000000000000000000000001000>;
+v0x55d8003601f0_0 .net "clk", 0 0, v0x55d800374740_0;  1 drivers
+v0x55d800374510_0 .var "out", 8 0;
+v0x55d8003745f0_0 .net "reset", 0 0, v0x55d800374810_0;  1 drivers
+E_0x55d800360e90 .event posedge, v0x55d8003745f0_0, v0x55d8003601f0_0;
+    .scope S_0x55d800361cd0;
+T_0 ;
+    %wait E_0x55d800360e90;
+    %load/vec4 v0x55d8003745f0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_0.0, 8;
+    %pushi/vec4 0, 0, 9;
+    %assign/vec4 v0x55d800374510_0, 0;
+    %jmp T_0.1;
+T_0.0 ;
+    %load/vec4 v0x55d800374510_0;
+    %addi 1, 0, 9;
+    %assign/vec4 v0x55d800374510_0, 0;
+T_0.1 ;
+    %jmp T_0;
+    .thread T_0;
+    .scope S_0x55d800361b40;
+T_1 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55d800374810_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55d800374740_0, 0, 1;
+    %end;
+    .thread T_1;
+    .scope S_0x55d800361b40;
+T_2 ;
+    %delay 17, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55d800374810_0, 0, 1;
+    %delay 11, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55d800374810_0, 0, 1;
+    %delay 29, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55d800374810_0, 0, 1;
+    %delay 11, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55d800374810_0, 0, 1;
+    %delay 100, 0;
+    %vpi_call 2 10 "$stop" {0 0 0};
+    %end;
+    .thread T_2;
+    .scope S_0x55d800361b40;
+T_3 ;
+    %delay 5, 0;
+    %load/vec4 v0x55d800374740_0;
+    %nor/r;
+    %store/vec4 v0x55d800374740_0, 0, 1;
+    %jmp T_3;
+    .thread T_3;
+    .scope S_0x55d800361b40;
+T_4 ;
+    %vpi_call 2 21 "$monitor", "At time %t, value = %h (%0d)", $time, v0x55d8003748e0_0, v0x55d8003748e0_0 {0 0 0};
+    %end;
+    .thread T_4;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "counter_tb.v";
+    "counter.v";

verilog_iverilog/counter/counter_tb.v

@@ -0,0 +1,23 @@
+module test;
+
+  /* Make a reset that pulses once. */
+  reg reset = 0;
+  initial begin
+     # 17 reset = 1;
+     # 11 reset = 0;
+     # 29 reset = 1;
+     # 11 reset = 0;
+     # 100 $stop;
+  end
+
+  /* Make a regular pulsing clock. */
+  reg clk = 0;
+  always #5 clk = !clk;
+
+  wire [7:0] value;
+  counter c1 (value, clk, reset);
+
+  initial
+     $monitor("At time %t, value = %h (%0d)",
+              $time, value, value);
+endmodule // test

verilog_iverilog/hello_world/Makefile

@@ -0,0 +1,5 @@
+run: hello.vvp
+	vvp $<
+
+%.vvp : %.v
+	iverilog $< -o $@

verilog_iverilog/hello_world/hello.v

@@ -0,0 +1,7 @@
+module hello;
+initial 
+begin
+	$display("Hello, World");
+	$finish ;
+end
+endmodule

verilog_iverilog/hello_world/hello.vvp

@@ -0,0 +1,22 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x561cd5980760 .scope module, "hello" "hello" 2 1;
+ .timescale 0 0;
+    .scope S_0x561cd5980760;
+T_0 ;
+    %vpi_call 2 4 "$display", "Hello, World" {0 0 0};
+    %vpi_call 2 5 "$finish" {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 3;
+    "N/A";
+    "<interactive>";
+    "hello.v";