Added clock and gtkwave integration
This commit is contained in:
parent
b749a5610e
commit
d8f6c595a2
2
.gitignore
vendored
2
.gitignore
vendored
@ -1,2 +1,4 @@
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*.vvp
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*.vvp
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*.vpi
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*.lx2
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*.o
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*.o
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@ -12,4 +12,4 @@ simulate: ${OBJECTS}
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iverilog $^ -o $@
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iverilog $^ -o $@
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clean:
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clean:
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rm ${OBJECTS} -f
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rm ${OBJECTS} hello.vpi -f
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18
verilog_iverilog/clock/Makefile
Normal file
18
verilog_iverilog/clock/Makefile
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@ -0,0 +1,18 @@
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SOURCES=clock.v clock-tb.v
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VPP=clock.vpp
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.PHONY: run
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run: ${VPP}
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vvp ${VPP}
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.PHONY: wave
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wave: ${VPP}
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vvp ${VPP} -lxt2
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gtkwave test.lx2 gtkwave_savefile.gtkw
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${VPP} : ${SOURCES}
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iverilog -g2012 $^ -o $@
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.PHONY: clean
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clean:
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rm -f ${VPP} test.lx2
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28
verilog_iverilog/clock/clock-tb.v
Normal file
28
verilog_iverilog/clock/clock-tb.v
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@ -0,0 +1,28 @@
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module tb;
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wire clk1;
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wire clk2;
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wire clk3;
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wire clk4;
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reg enable;
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reg [7:0] delay;
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clock_gen u0(enable, clk1);
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clock_gen #(.FREQ(100000)) u1(enable, clk2);
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clock_gen #(.FREQ(200000)) u2(enable, clk3);
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clock_gen #(.FREQ(400000)) u3(enable, clk4);
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integer i ;
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initial begin
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$dumpfile("test.lx2");
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$dumpvars(0,u1,u2,u3);
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enable <= 0;
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for ( i = 0; i < 10; i=i+1) begin
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delay = $random;
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#(delay) enable <= ~enable;
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$display("i=%0d delay=%0d", i, delay);
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#50;
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end
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#50 $finish;
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end
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endmodule
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61
verilog_iverilog/clock/clock.v
Normal file
61
verilog_iverilog/clock/clock.v
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@ -0,0 +1,61 @@
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`timescale 1ns/1ps
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module clock_gen (input enable, output reg clk);
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parameter FREQ = 1000; // in HZ
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parameter PHASE = 0; // in degrees
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parameter DUTY = 50; // in percentage
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real clk_pd = 1.0/FREQ * 1000000; // convert to ns
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real clk_on = DUTY/100.0 * clk_pd;
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real clk_off = (100.0 - DUTY)/100.0 * clk_pd;
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real quarter = clk_pd/4;
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real start_dly = quarter * PHASE/90;
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reg start_clk;
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initial begin
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$display("FREQ = %0d kHz", FREQ);
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$display("PHASE = %0d deg", PHASE);
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$display("DUTY = %0d %%", DUTY);
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$display("PERIOD = %0.1f ms", clk_pd);
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$display("CLK_ON = %0.1f ms", clk_on);
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$display("CLK_OFF = %0.1f ms", clk_off);
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$display("QUARTER = %0.1f ms", quarter);
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$display("START_DLY = %0.1f ms", start_dly);
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end
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// Initialize variables to zero
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initial begin
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clk <= 0;
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start_clk <= 0;
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end
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// When clock is enabled, delay driving the clock to one in order
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// to achieve the phase effect. start_dly is configured to the
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// correct delay for the configured phase. When enable is 0,
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// allow enough time to complete the current clock period
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always @ (posedge enable or negedge enable) begin
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if (enable) begin
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#(start_dly) start_clk = 1;
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end else begin
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#(start_dly) start_clk = 0;
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end
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end
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// Achieve duty cycle by a skewed clock on/off time and let this
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// run as long as the clocks are turned on.
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always @(posedge start_clk) begin
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if (start_clk) begin
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clk = 1;
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while (start_clk) begin
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#(clk_on) clk = 0;
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#(clk_off) clk = 1;
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end
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clk = 0;
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end
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end
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endmodule
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581
verilog_iverilog/clock/clock.vpp
Executable file
581
verilog_iverilog/clock/clock.vpp
Executable file
@ -0,0 +1,581 @@
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#! /usr/bin/vvp
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:ivl_version "11.0 (stable)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision - 12;
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2009.vpi";
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S_0x5610fda4b6d0 .scope package, "$unit" "$unit" 2 1;
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.timescale 0 0;
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S_0x5610fda4b860 .scope module, "tb" "tb" 3 1;
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.timescale -9 -12;
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v0x5610fda78da0_0 .net "clk1", 0 0, v0x5610fda53880_0; 1 drivers
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v0x5610fda78e40_0 .net "clk2", 0 0, v0x5610fda76fe0_0; 1 drivers
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v0x5610fda78f10_0 .net "clk3", 0 0, v0x5610fda77b40_0; 1 drivers
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v0x5610fda79010_0 .net "clk4", 0 0, v0x5610fda786e0_0; 1 drivers
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v0x5610fda790e0_0 .var "delay", 7 0;
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v0x5610fda791d0_0 .var "enable", 0 0;
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v0x5610fda79270_0 .var/i "i", 31 0;
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S_0x5610fda44700 .scope module, "u0" "clock_gen" 3 9, 4 3 0, S_0x5610fda4b860;
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.timescale -9 -12;
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.port_info 0 /INPUT 1 "enable";
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.port_info 1 /OUTPUT 1 "clk";
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P_0x5610fda0ca60 .param/l "DUTY" 0 4 7, +C4<00000000000000000000000000110010>;
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P_0x5610fda0caa0 .param/l "FREQ" 0 4 5, +C4<00000000000000000000001111101000>;
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P_0x5610fda0cae0 .param/l "PHASE" 0 4 6, +C4<00000000000000000000000000000000>;
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v0x5610fda53880_0 .var "clk", 0 0;
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v0x5610fda53920_0 .var/real "clk_off", 0 0;
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v0x5610fda42f50_0 .var/real "clk_on", 0 0;
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v0x5610fda42ff0_0 .var/real "clk_pd", 0 0;
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v0x5610fda3e7e0_0 .net "enable", 0 0, v0x5610fda791d0_0; 1 drivers
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v0x5610fda3e880_0 .var/real "quarter", 0 0;
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v0x5610fda769f0_0 .var "start_clk", 0 0;
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v0x5610fda76ab0_0 .var/real "start_dly", 0 0;
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E_0x5610fda468c0 .event posedge, v0x5610fda769f0_0;
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E_0x5610fda47160/0 .event negedge, v0x5610fda3e7e0_0;
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E_0x5610fda47160/1 .event posedge, v0x5610fda3e7e0_0;
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E_0x5610fda47160 .event/or E_0x5610fda47160/0, E_0x5610fda47160/1;
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S_0x5610fda76bd0 .scope module, "u1" "clock_gen" 3 10, 4 3 0, S_0x5610fda4b860;
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.timescale -9 -12;
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.port_info 0 /INPUT 1 "enable";
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.port_info 1 /OUTPUT 1 "clk";
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P_0x5610fda76db0 .param/l "DUTY" 0 4 7, +C4<00000000000000000000000000110010>;
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P_0x5610fda76df0 .param/l "FREQ" 0 4 5, +C4<00000000000000011000011010100000>;
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P_0x5610fda76e30 .param/l "PHASE" 0 4 6, +C4<00000000000000000000000000000000>;
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v0x5610fda76fe0_0 .var "clk", 0 0;
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v0x5610fda770c0_0 .var/real "clk_off", 0 0;
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v0x5610fda77180_0 .var/real "clk_on", 0 0;
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v0x5610fda77250_0 .var/real "clk_pd", 0 0;
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v0x5610fda77310_0 .net "enable", 0 0, v0x5610fda791d0_0; alias, 1 drivers
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v0x5610fda77400_0 .var/real "quarter", 0 0;
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v0x5610fda774a0_0 .var "start_clk", 0 0;
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v0x5610fda77560_0 .var/real "start_dly", 0 0;
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E_0x5610fda2f6d0 .event posedge, v0x5610fda774a0_0;
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S_0x5610fda77680 .scope module, "u2" "clock_gen" 3 11, 4 3 0, S_0x5610fda4b860;
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.timescale -9 -12;
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.port_info 0 /INPUT 1 "enable";
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.port_info 1 /OUTPUT 1 "clk";
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P_0x5610fda77890 .param/l "DUTY" 0 4 7, +C4<00000000000000000000000000110010>;
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P_0x5610fda778d0 .param/l "FREQ" 0 4 5, +C4<00000000000000110000110101000000>;
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P_0x5610fda77910 .param/l "PHASE" 0 4 6, +C4<00000000000000000000000000000000>;
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v0x5610fda77b40_0 .var "clk", 0 0;
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v0x5610fda77c20_0 .var/real "clk_off", 0 0;
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v0x5610fda77ce0_0 .var/real "clk_on", 0 0;
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v0x5610fda77db0_0 .var/real "clk_pd", 0 0;
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v0x5610fda77e70_0 .net "enable", 0 0, v0x5610fda791d0_0; alias, 1 drivers
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v0x5610fda77fb0_0 .var/real "quarter", 0 0;
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v0x5610fda78070_0 .var "start_clk", 0 0;
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v0x5610fda78130_0 .var/real "start_dly", 0 0;
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E_0x5610fda77ae0 .event posedge, v0x5610fda78070_0;
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S_0x5610fda78250 .scope module, "u3" "clock_gen" 3 12, 4 3 0, S_0x5610fda4b860;
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.timescale -9 -12;
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.port_info 0 /INPUT 1 "enable";
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.port_info 1 /OUTPUT 1 "clk";
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P_0x5610fda78430 .param/l "DUTY" 0 4 7, +C4<00000000000000000000000000110010>;
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P_0x5610fda78470 .param/l "FREQ" 0 4 5, +C4<00000000000001100001101010000000>;
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P_0x5610fda784b0 .param/l "PHASE" 0 4 6, +C4<00000000000000000000000000000000>;
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v0x5610fda786e0_0 .var "clk", 0 0;
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v0x5610fda787c0_0 .var/real "clk_off", 0 0;
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v0x5610fda78880_0 .var/real "clk_on", 0 0;
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v0x5610fda78950_0 .var/real "clk_pd", 0 0;
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v0x5610fda78a10_0 .net "enable", 0 0, v0x5610fda791d0_0; alias, 1 drivers
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v0x5610fda78b00_0 .var/real "quarter", 0 0;
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v0x5610fda78bc0_0 .var "start_clk", 0 0;
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v0x5610fda78c80_0 .var/real "start_dly", 0 0;
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E_0x5610fda78660 .event posedge, v0x5610fda78bc0_0;
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.scope S_0x5610fda44700;
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T_0 ;
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%pushi/real 2097152000, 4075; load=1000.00
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%store/real v0x5610fda42ff0_0;
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%pushi/real 1073741824, 4065; load=0.500000
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%load/real v0x5610fda42ff0_0;
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%mul/wr;
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%store/real v0x5610fda42f50_0;
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%pushi/real 1073741824, 4065; load=0.500000
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%load/real v0x5610fda42ff0_0;
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%mul/wr;
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%store/real v0x5610fda53920_0;
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%load/real v0x5610fda42ff0_0;
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%pushi/vec4 4, 0, 32;
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%cvt/rv/s;
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%div/wr;
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%store/real v0x5610fda3e880_0;
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%load/real v0x5610fda3e880_0;
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%pushi/vec4 0, 0, 32;
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%cvt/rv/s;
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%mul/wr;
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%pushi/vec4 90, 0, 32;
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%cvt/rv/s;
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%div/wr;
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%store/real v0x5610fda76ab0_0;
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%end;
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.thread T_0, $init;
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.scope S_0x5610fda44700;
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T_1 ;
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%vpi_call/w 4 18 "$display", "FREQ = %0d kHz", P_0x5610fda0caa0 {0 0 0};
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%vpi_call/w 4 19 "$display", "PHASE = %0d deg", P_0x5610fda0cae0 {0 0 0};
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%vpi_call/w 4 20 "$display", "DUTY = %0d %%", P_0x5610fda0ca60 {0 0 0};
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%vpi_call/w 4 22 "$display", "PERIOD = %0.1f ms", v0x5610fda42ff0_0 {0 0 0};
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%vpi_call/w 4 23 "$display", "CLK_ON = %0.1f ms", v0x5610fda42f50_0 {0 0 0};
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%vpi_call/w 4 24 "$display", "CLK_OFF = %0.1f ms", v0x5610fda53920_0 {0 0 0};
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%vpi_call/w 4 25 "$display", "QUARTER = %0.1f ms", v0x5610fda3e880_0 {0 0 0};
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%vpi_call/w 4 26 "$display", "START_DLY = %0.1f ms", v0x5610fda76ab0_0 {0 0 0};
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%end;
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.thread T_1;
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.scope S_0x5610fda44700;
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T_2 ;
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%pushi/vec4 0, 0, 1;
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%assign/vec4 v0x5610fda53880_0, 0;
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%pushi/vec4 0, 0, 1;
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%assign/vec4 v0x5610fda769f0_0, 0;
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%end;
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.thread T_2;
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.scope S_0x5610fda44700;
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T_3 ;
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%wait E_0x5610fda47160;
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%load/vec4 v0x5610fda3e7e0_0;
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%flag_set/vec4 8;
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%jmp/0xz T_3.0, 8;
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%load/real v0x5610fda76ab0_0;
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%pushi/real 2097152000, 4075; load=1000.00
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%mul/wr;
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%cvt/vr 64;
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%muli 1, 0, 64;
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%ix/vec4 4;
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%delayx 4;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x5610fda769f0_0, 0, 1;
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%jmp T_3.1;
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T_3.0 ;
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%load/real v0x5610fda76ab0_0;
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%pushi/real 2097152000, 4075; load=1000.00
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%mul/wr;
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%cvt/vr 64;
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%muli 1, 0, 64;
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%ix/vec4 4;
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%delayx 4;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x5610fda769f0_0, 0, 1;
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T_3.1 ;
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%jmp T_3;
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.thread T_3;
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.scope S_0x5610fda44700;
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T_4 ;
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%wait E_0x5610fda468c0;
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%load/vec4 v0x5610fda769f0_0;
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%flag_set/vec4 8;
|
||||||
|
%jmp/0xz T_4.0, 8;
|
||||||
|
%pushi/vec4 1, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda53880_0, 0, 1;
|
||||||
|
T_4.2 ;
|
||||||
|
%load/vec4 v0x5610fda769f0_0;
|
||||||
|
%flag_set/vec4 8;
|
||||||
|
%jmp/0xz T_4.3, 8;
|
||||||
|
%load/real v0x5610fda42f50_0;
|
||||||
|
%pushi/real 2097152000, 4075; load=1000.00
|
||||||
|
%mul/wr;
|
||||||
|
%cvt/vr 64;
|
||||||
|
%muli 1, 0, 64;
|
||||||
|
%ix/vec4 4;
|
||||||
|
%delayx 4;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda53880_0, 0, 1;
|
||||||
|
%load/real v0x5610fda53920_0;
|
||||||
|
%pushi/real 2097152000, 4075; load=1000.00
|
||||||
|
%mul/wr;
|
||||||
|
%cvt/vr 64;
|
||||||
|
%muli 1, 0, 64;
|
||||||
|
%ix/vec4 4;
|
||||||
|
%delayx 4;
|
||||||
|
%pushi/vec4 1, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda53880_0, 0, 1;
|
||||||
|
%jmp T_4.2;
|
||||||
|
T_4.3 ;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda53880_0, 0, 1;
|
||||||
|
T_4.0 ;
|
||||||
|
%jmp T_4;
|
||||||
|
.thread T_4;
|
||||||
|
.scope S_0x5610fda76bd0;
|
||||||
|
T_5 ;
|
||||||
|
%pushi/real 1342177280, 4069; load=10.0000
|
||||||
|
%store/real v0x5610fda77250_0;
|
||||||
|
%pushi/real 1073741824, 4065; load=0.500000
|
||||||
|
%load/real v0x5610fda77250_0;
|
||||||
|
%mul/wr;
|
||||||
|
%store/real v0x5610fda77180_0;
|
||||||
|
%pushi/real 1073741824, 4065; load=0.500000
|
||||||
|
%load/real v0x5610fda77250_0;
|
||||||
|
%mul/wr;
|
||||||
|
%store/real v0x5610fda770c0_0;
|
||||||
|
%load/real v0x5610fda77250_0;
|
||||||
|
%pushi/vec4 4, 0, 32;
|
||||||
|
%cvt/rv/s;
|
||||||
|
%div/wr;
|
||||||
|
%store/real v0x5610fda77400_0;
|
||||||
|
%load/real v0x5610fda77400_0;
|
||||||
|
%pushi/vec4 0, 0, 32;
|
||||||
|
%cvt/rv/s;
|
||||||
|
%mul/wr;
|
||||||
|
%pushi/vec4 90, 0, 32;
|
||||||
|
%cvt/rv/s;
|
||||||
|
%div/wr;
|
||||||
|
%store/real v0x5610fda77560_0;
|
||||||
|
%end;
|
||||||
|
.thread T_5, $init;
|
||||||
|
.scope S_0x5610fda76bd0;
|
||||||
|
T_6 ;
|
||||||
|
%vpi_call/w 4 18 "$display", "FREQ = %0d kHz", P_0x5610fda76df0 {0 0 0};
|
||||||
|
%vpi_call/w 4 19 "$display", "PHASE = %0d deg", P_0x5610fda76e30 {0 0 0};
|
||||||
|
%vpi_call/w 4 20 "$display", "DUTY = %0d %%", P_0x5610fda76db0 {0 0 0};
|
||||||
|
%vpi_call/w 4 22 "$display", "PERIOD = %0.1f ms", v0x5610fda77250_0 {0 0 0};
|
||||||
|
%vpi_call/w 4 23 "$display", "CLK_ON = %0.1f ms", v0x5610fda77180_0 {0 0 0};
|
||||||
|
%vpi_call/w 4 24 "$display", "CLK_OFF = %0.1f ms", v0x5610fda770c0_0 {0 0 0};
|
||||||
|
%vpi_call/w 4 25 "$display", "QUARTER = %0.1f ms", v0x5610fda77400_0 {0 0 0};
|
||||||
|
%vpi_call/w 4 26 "$display", "START_DLY = %0.1f ms", v0x5610fda77560_0 {0 0 0};
|
||||||
|
%end;
|
||||||
|
.thread T_6;
|
||||||
|
.scope S_0x5610fda76bd0;
|
||||||
|
T_7 ;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%assign/vec4 v0x5610fda76fe0_0, 0;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%assign/vec4 v0x5610fda774a0_0, 0;
|
||||||
|
%end;
|
||||||
|
.thread T_7;
|
||||||
|
.scope S_0x5610fda76bd0;
|
||||||
|
T_8 ;
|
||||||
|
%wait E_0x5610fda47160;
|
||||||
|
%load/vec4 v0x5610fda77310_0;
|
||||||
|
%flag_set/vec4 8;
|
||||||
|
%jmp/0xz T_8.0, 8;
|
||||||
|
%load/real v0x5610fda77560_0;
|
||||||
|
%pushi/real 2097152000, 4075; load=1000.00
|
||||||
|
%mul/wr;
|
||||||
|
%cvt/vr 64;
|
||||||
|
%muli 1, 0, 64;
|
||||||
|
%ix/vec4 4;
|
||||||
|
%delayx 4;
|
||||||
|
%pushi/vec4 1, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda774a0_0, 0, 1;
|
||||||
|
%jmp T_8.1;
|
||||||
|
T_8.0 ;
|
||||||
|
%load/real v0x5610fda77560_0;
|
||||||
|
%pushi/real 2097152000, 4075; load=1000.00
|
||||||
|
%mul/wr;
|
||||||
|
%cvt/vr 64;
|
||||||
|
%muli 1, 0, 64;
|
||||||
|
%ix/vec4 4;
|
||||||
|
%delayx 4;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda774a0_0, 0, 1;
|
||||||
|
T_8.1 ;
|
||||||
|
%jmp T_8;
|
||||||
|
.thread T_8;
|
||||||
|
.scope S_0x5610fda76bd0;
|
||||||
|
T_9 ;
|
||||||
|
%wait E_0x5610fda2f6d0;
|
||||||
|
%load/vec4 v0x5610fda774a0_0;
|
||||||
|
%flag_set/vec4 8;
|
||||||
|
%jmp/0xz T_9.0, 8;
|
||||||
|
%pushi/vec4 1, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda76fe0_0, 0, 1;
|
||||||
|
T_9.2 ;
|
||||||
|
%load/vec4 v0x5610fda774a0_0;
|
||||||
|
%flag_set/vec4 8;
|
||||||
|
%jmp/0xz T_9.3, 8;
|
||||||
|
%load/real v0x5610fda77180_0;
|
||||||
|
%pushi/real 2097152000, 4075; load=1000.00
|
||||||
|
%mul/wr;
|
||||||
|
%cvt/vr 64;
|
||||||
|
%muli 1, 0, 64;
|
||||||
|
%ix/vec4 4;
|
||||||
|
%delayx 4;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda76fe0_0, 0, 1;
|
||||||
|
%load/real v0x5610fda770c0_0;
|
||||||
|
%pushi/real 2097152000, 4075; load=1000.00
|
||||||
|
%mul/wr;
|
||||||
|
%cvt/vr 64;
|
||||||
|
%muli 1, 0, 64;
|
||||||
|
%ix/vec4 4;
|
||||||
|
%delayx 4;
|
||||||
|
%pushi/vec4 1, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda76fe0_0, 0, 1;
|
||||||
|
%jmp T_9.2;
|
||||||
|
T_9.3 ;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda76fe0_0, 0, 1;
|
||||||
|
T_9.0 ;
|
||||||
|
%jmp T_9;
|
||||||
|
.thread T_9;
|
||||||
|
.scope S_0x5610fda77680;
|
||||||
|
T_10 ;
|
||||||
|
%pushi/real 1342177280, 4068; load=5.00000
|
||||||
|
%store/real v0x5610fda77db0_0;
|
||||||
|
%pushi/real 1073741824, 4065; load=0.500000
|
||||||
|
%load/real v0x5610fda77db0_0;
|
||||||
|
%mul/wr;
|
||||||
|
%store/real v0x5610fda77ce0_0;
|
||||||
|
%pushi/real 1073741824, 4065; load=0.500000
|
||||||
|
%load/real v0x5610fda77db0_0;
|
||||||
|
%mul/wr;
|
||||||
|
%store/real v0x5610fda77c20_0;
|
||||||
|
%load/real v0x5610fda77db0_0;
|
||||||
|
%pushi/vec4 4, 0, 32;
|
||||||
|
%cvt/rv/s;
|
||||||
|
%div/wr;
|
||||||
|
%store/real v0x5610fda77fb0_0;
|
||||||
|
%load/real v0x5610fda77fb0_0;
|
||||||
|
%pushi/vec4 0, 0, 32;
|
||||||
|
%cvt/rv/s;
|
||||||
|
%mul/wr;
|
||||||
|
%pushi/vec4 90, 0, 32;
|
||||||
|
%cvt/rv/s;
|
||||||
|
%div/wr;
|
||||||
|
%store/real v0x5610fda78130_0;
|
||||||
|
%end;
|
||||||
|
.thread T_10, $init;
|
||||||
|
.scope S_0x5610fda77680;
|
||||||
|
T_11 ;
|
||||||
|
%vpi_call/w 4 18 "$display", "FREQ = %0d kHz", P_0x5610fda778d0 {0 0 0};
|
||||||
|
%vpi_call/w 4 19 "$display", "PHASE = %0d deg", P_0x5610fda77910 {0 0 0};
|
||||||
|
%vpi_call/w 4 20 "$display", "DUTY = %0d %%", P_0x5610fda77890 {0 0 0};
|
||||||
|
%vpi_call/w 4 22 "$display", "PERIOD = %0.1f ms", v0x5610fda77db0_0 {0 0 0};
|
||||||
|
%vpi_call/w 4 23 "$display", "CLK_ON = %0.1f ms", v0x5610fda77ce0_0 {0 0 0};
|
||||||
|
%vpi_call/w 4 24 "$display", "CLK_OFF = %0.1f ms", v0x5610fda77c20_0 {0 0 0};
|
||||||
|
%vpi_call/w 4 25 "$display", "QUARTER = %0.1f ms", v0x5610fda77fb0_0 {0 0 0};
|
||||||
|
%vpi_call/w 4 26 "$display", "START_DLY = %0.1f ms", v0x5610fda78130_0 {0 0 0};
|
||||||
|
%end;
|
||||||
|
.thread T_11;
|
||||||
|
.scope S_0x5610fda77680;
|
||||||
|
T_12 ;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%assign/vec4 v0x5610fda77b40_0, 0;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%assign/vec4 v0x5610fda78070_0, 0;
|
||||||
|
%end;
|
||||||
|
.thread T_12;
|
||||||
|
.scope S_0x5610fda77680;
|
||||||
|
T_13 ;
|
||||||
|
%wait E_0x5610fda47160;
|
||||||
|
%load/vec4 v0x5610fda77e70_0;
|
||||||
|
%flag_set/vec4 8;
|
||||||
|
%jmp/0xz T_13.0, 8;
|
||||||
|
%load/real v0x5610fda78130_0;
|
||||||
|
%pushi/real 2097152000, 4075; load=1000.00
|
||||||
|
%mul/wr;
|
||||||
|
%cvt/vr 64;
|
||||||
|
%muli 1, 0, 64;
|
||||||
|
%ix/vec4 4;
|
||||||
|
%delayx 4;
|
||||||
|
%pushi/vec4 1, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda78070_0, 0, 1;
|
||||||
|
%jmp T_13.1;
|
||||||
|
T_13.0 ;
|
||||||
|
%load/real v0x5610fda78130_0;
|
||||||
|
%pushi/real 2097152000, 4075; load=1000.00
|
||||||
|
%mul/wr;
|
||||||
|
%cvt/vr 64;
|
||||||
|
%muli 1, 0, 64;
|
||||||
|
%ix/vec4 4;
|
||||||
|
%delayx 4;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda78070_0, 0, 1;
|
||||||
|
T_13.1 ;
|
||||||
|
%jmp T_13;
|
||||||
|
.thread T_13;
|
||||||
|
.scope S_0x5610fda77680;
|
||||||
|
T_14 ;
|
||||||
|
%wait E_0x5610fda77ae0;
|
||||||
|
%load/vec4 v0x5610fda78070_0;
|
||||||
|
%flag_set/vec4 8;
|
||||||
|
%jmp/0xz T_14.0, 8;
|
||||||
|
%pushi/vec4 1, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda77b40_0, 0, 1;
|
||||||
|
T_14.2 ;
|
||||||
|
%load/vec4 v0x5610fda78070_0;
|
||||||
|
%flag_set/vec4 8;
|
||||||
|
%jmp/0xz T_14.3, 8;
|
||||||
|
%load/real v0x5610fda77ce0_0;
|
||||||
|
%pushi/real 2097152000, 4075; load=1000.00
|
||||||
|
%mul/wr;
|
||||||
|
%cvt/vr 64;
|
||||||
|
%muli 1, 0, 64;
|
||||||
|
%ix/vec4 4;
|
||||||
|
%delayx 4;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda77b40_0, 0, 1;
|
||||||
|
%load/real v0x5610fda77c20_0;
|
||||||
|
%pushi/real 2097152000, 4075; load=1000.00
|
||||||
|
%mul/wr;
|
||||||
|
%cvt/vr 64;
|
||||||
|
%muli 1, 0, 64;
|
||||||
|
%ix/vec4 4;
|
||||||
|
%delayx 4;
|
||||||
|
%pushi/vec4 1, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda77b40_0, 0, 1;
|
||||||
|
%jmp T_14.2;
|
||||||
|
T_14.3 ;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda77b40_0, 0, 1;
|
||||||
|
T_14.0 ;
|
||||||
|
%jmp T_14;
|
||||||
|
.thread T_14;
|
||||||
|
.scope S_0x5610fda78250;
|
||||||
|
T_15 ;
|
||||||
|
%pushi/real 1342177280, 4067; load=2.50000
|
||||||
|
%store/real v0x5610fda78950_0;
|
||||||
|
%pushi/real 1073741824, 4065; load=0.500000
|
||||||
|
%load/real v0x5610fda78950_0;
|
||||||
|
%mul/wr;
|
||||||
|
%store/real v0x5610fda78880_0;
|
||||||
|
%pushi/real 1073741824, 4065; load=0.500000
|
||||||
|
%load/real v0x5610fda78950_0;
|
||||||
|
%mul/wr;
|
||||||
|
%store/real v0x5610fda787c0_0;
|
||||||
|
%load/real v0x5610fda78950_0;
|
||||||
|
%pushi/vec4 4, 0, 32;
|
||||||
|
%cvt/rv/s;
|
||||||
|
%div/wr;
|
||||||
|
%store/real v0x5610fda78b00_0;
|
||||||
|
%load/real v0x5610fda78b00_0;
|
||||||
|
%pushi/vec4 0, 0, 32;
|
||||||
|
%cvt/rv/s;
|
||||||
|
%mul/wr;
|
||||||
|
%pushi/vec4 90, 0, 32;
|
||||||
|
%cvt/rv/s;
|
||||||
|
%div/wr;
|
||||||
|
%store/real v0x5610fda78c80_0;
|
||||||
|
%end;
|
||||||
|
.thread T_15, $init;
|
||||||
|
.scope S_0x5610fda78250;
|
||||||
|
T_16 ;
|
||||||
|
%vpi_call/w 4 18 "$display", "FREQ = %0d kHz", P_0x5610fda78470 {0 0 0};
|
||||||
|
%vpi_call/w 4 19 "$display", "PHASE = %0d deg", P_0x5610fda784b0 {0 0 0};
|
||||||
|
%vpi_call/w 4 20 "$display", "DUTY = %0d %%", P_0x5610fda78430 {0 0 0};
|
||||||
|
%vpi_call/w 4 22 "$display", "PERIOD = %0.1f ms", v0x5610fda78950_0 {0 0 0};
|
||||||
|
%vpi_call/w 4 23 "$display", "CLK_ON = %0.1f ms", v0x5610fda78880_0 {0 0 0};
|
||||||
|
%vpi_call/w 4 24 "$display", "CLK_OFF = %0.1f ms", v0x5610fda787c0_0 {0 0 0};
|
||||||
|
%vpi_call/w 4 25 "$display", "QUARTER = %0.1f ms", v0x5610fda78b00_0 {0 0 0};
|
||||||
|
%vpi_call/w 4 26 "$display", "START_DLY = %0.1f ms", v0x5610fda78c80_0 {0 0 0};
|
||||||
|
%end;
|
||||||
|
.thread T_16;
|
||||||
|
.scope S_0x5610fda78250;
|
||||||
|
T_17 ;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%assign/vec4 v0x5610fda786e0_0, 0;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%assign/vec4 v0x5610fda78bc0_0, 0;
|
||||||
|
%end;
|
||||||
|
.thread T_17;
|
||||||
|
.scope S_0x5610fda78250;
|
||||||
|
T_18 ;
|
||||||
|
%wait E_0x5610fda47160;
|
||||||
|
%load/vec4 v0x5610fda78a10_0;
|
||||||
|
%flag_set/vec4 8;
|
||||||
|
%jmp/0xz T_18.0, 8;
|
||||||
|
%load/real v0x5610fda78c80_0;
|
||||||
|
%pushi/real 2097152000, 4075; load=1000.00
|
||||||
|
%mul/wr;
|
||||||
|
%cvt/vr 64;
|
||||||
|
%muli 1, 0, 64;
|
||||||
|
%ix/vec4 4;
|
||||||
|
%delayx 4;
|
||||||
|
%pushi/vec4 1, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda78bc0_0, 0, 1;
|
||||||
|
%jmp T_18.1;
|
||||||
|
T_18.0 ;
|
||||||
|
%load/real v0x5610fda78c80_0;
|
||||||
|
%pushi/real 2097152000, 4075; load=1000.00
|
||||||
|
%mul/wr;
|
||||||
|
%cvt/vr 64;
|
||||||
|
%muli 1, 0, 64;
|
||||||
|
%ix/vec4 4;
|
||||||
|
%delayx 4;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda78bc0_0, 0, 1;
|
||||||
|
T_18.1 ;
|
||||||
|
%jmp T_18;
|
||||||
|
.thread T_18;
|
||||||
|
.scope S_0x5610fda78250;
|
||||||
|
T_19 ;
|
||||||
|
%wait E_0x5610fda78660;
|
||||||
|
%load/vec4 v0x5610fda78bc0_0;
|
||||||
|
%flag_set/vec4 8;
|
||||||
|
%jmp/0xz T_19.0, 8;
|
||||||
|
%pushi/vec4 1, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda786e0_0, 0, 1;
|
||||||
|
T_19.2 ;
|
||||||
|
%load/vec4 v0x5610fda78bc0_0;
|
||||||
|
%flag_set/vec4 8;
|
||||||
|
%jmp/0xz T_19.3, 8;
|
||||||
|
%load/real v0x5610fda78880_0;
|
||||||
|
%pushi/real 2097152000, 4075; load=1000.00
|
||||||
|
%mul/wr;
|
||||||
|
%cvt/vr 64;
|
||||||
|
%muli 1, 0, 64;
|
||||||
|
%ix/vec4 4;
|
||||||
|
%delayx 4;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda786e0_0, 0, 1;
|
||||||
|
%load/real v0x5610fda787c0_0;
|
||||||
|
%pushi/real 2097152000, 4075; load=1000.00
|
||||||
|
%mul/wr;
|
||||||
|
%cvt/vr 64;
|
||||||
|
%muli 1, 0, 64;
|
||||||
|
%ix/vec4 4;
|
||||||
|
%delayx 4;
|
||||||
|
%pushi/vec4 1, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda786e0_0, 0, 1;
|
||||||
|
%jmp T_19.2;
|
||||||
|
T_19.3 ;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%store/vec4 v0x5610fda786e0_0, 0, 1;
|
||||||
|
T_19.0 ;
|
||||||
|
%jmp T_19;
|
||||||
|
.thread T_19;
|
||||||
|
.scope S_0x5610fda4b860;
|
||||||
|
T_20 ;
|
||||||
|
%vpi_call/w 3 15 "$dumpfile", "test.lx2" {0 0 0};
|
||||||
|
%vpi_call/w 3 16 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x5610fda76bd0, S_0x5610fda77680, S_0x5610fda78250 {0 0 0};
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%assign/vec4 v0x5610fda791d0_0, 0;
|
||||||
|
%pushi/vec4 0, 0, 32;
|
||||||
|
%store/vec4 v0x5610fda79270_0, 0, 32;
|
||||||
|
T_20.0 ;
|
||||||
|
%load/vec4 v0x5610fda79270_0;
|
||||||
|
%cmpi/s 10, 0, 32;
|
||||||
|
%jmp/0xz T_20.1, 5;
|
||||||
|
%vpi_func 3 20 "$random" 32 {0 0 0};
|
||||||
|
%pad/s 8;
|
||||||
|
%store/vec4 v0x5610fda790e0_0, 0, 8;
|
||||||
|
%load/vec4 v0x5610fda790e0_0;
|
||||||
|
%pad/u 64;
|
||||||
|
%muli 1000, 0, 64;
|
||||||
|
%ix/vec4 4;
|
||||||
|
%delayx 4;
|
||||||
|
%load/vec4 v0x5610fda791d0_0;
|
||||||
|
%inv;
|
||||||
|
%assign/vec4 v0x5610fda791d0_0, 0;
|
||||||
|
%vpi_call/w 3 22 "$display", "i=%0d delay=%0d", v0x5610fda79270_0, v0x5610fda790e0_0 {0 0 0};
|
||||||
|
%delay 50000, 0;
|
||||||
|
%load/vec4 v0x5610fda79270_0;
|
||||||
|
%addi 1, 0, 32;
|
||||||
|
%store/vec4 v0x5610fda79270_0, 0, 32;
|
||||||
|
%jmp T_20.0;
|
||||||
|
T_20.1 ;
|
||||||
|
%delay 50000, 0;
|
||||||
|
%vpi_call/w 3 26 "$finish" {0 0 0};
|
||||||
|
%end;
|
||||||
|
.thread T_20;
|
||||||
|
# The file index is used to find the file name in the following table.
|
||||||
|
:file_names 5;
|
||||||
|
"N/A";
|
||||||
|
"<interactive>";
|
||||||
|
"-";
|
||||||
|
"clock-tb.v";
|
||||||
|
"clock.v";
|
||||||
27
verilog_iverilog/clock/gtkwave_savefile.gtkw
Normal file
27
verilog_iverilog/clock/gtkwave_savefile.gtkw
Normal file
@ -0,0 +1,27 @@
|
|||||||
|
[*]
|
||||||
|
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
|
||||||
|
[*] Tue Feb 7 17:50:40 2023
|
||||||
|
[*]
|
||||||
|
[dumpfile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/playground/verilog_iverilog/clock/test.lx2"
|
||||||
|
[dumpfile_mtime] "Tue Feb 7 17:49:38 2023"
|
||||||
|
[dumpfile_size] 4777
|
||||||
|
[savefile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/playground/verilog_iverilog/clock/gtkwave_savefile.gtkw"
|
||||||
|
[timestart] 0
|
||||||
|
[size] 1342 1059
|
||||||
|
[pos] -1 -1
|
||||||
|
*-17.808613 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||||
|
[treeopen] tb.
|
||||||
|
[sst_width] 221
|
||||||
|
[signals_width] 102
|
||||||
|
[sst_expanded] 1
|
||||||
|
[sst_vpaned_height] 313
|
||||||
|
@28
|
||||||
|
tb.u1.clk[0]
|
||||||
|
tb.u1.enable[0]
|
||||||
|
tb.u2.clk[0]
|
||||||
|
tb.u2.enable[0]
|
||||||
|
tb.u3.clk[0]
|
||||||
|
@29
|
||||||
|
tb.u3.enable[0]
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
||||||
Loading…
Reference in New Issue
Block a user