62 lines
1.7 KiB
Coq
62 lines
1.7 KiB
Coq
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`timescale 1ns/1ps
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module clock_gen (input enable, output reg clk);
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parameter FREQ = 1000; // in HZ
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parameter PHASE = 0; // in degrees
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parameter DUTY = 50; // in percentage
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real clk_pd = 1.0/FREQ * 1000000; // convert to ns
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real clk_on = DUTY/100.0 * clk_pd;
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real clk_off = (100.0 - DUTY)/100.0 * clk_pd;
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real quarter = clk_pd/4;
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real start_dly = quarter * PHASE/90;
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reg start_clk;
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initial begin
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$display("FREQ = %0d kHz", FREQ);
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$display("PHASE = %0d deg", PHASE);
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$display("DUTY = %0d %%", DUTY);
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$display("PERIOD = %0.1f ms", clk_pd);
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$display("CLK_ON = %0.1f ms", clk_on);
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$display("CLK_OFF = %0.1f ms", clk_off);
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$display("QUARTER = %0.1f ms", quarter);
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$display("START_DLY = %0.1f ms", start_dly);
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end
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// Initialize variables to zero
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initial begin
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clk <= 0;
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start_clk <= 0;
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end
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// When clock is enabled, delay driving the clock to one in order
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// to achieve the phase effect. start_dly is configured to the
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// correct delay for the configured phase. When enable is 0,
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// allow enough time to complete the current clock period
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always @ (posedge enable or negedge enable) begin
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if (enable) begin
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#(start_dly) start_clk = 1;
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end else begin
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#(start_dly) start_clk = 0;
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end
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end
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// Achieve duty cycle by a skewed clock on/off time and let this
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// run as long as the clocks are turned on.
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always @(posedge start_clk) begin
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if (start_clk) begin
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clk = 1;
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while (start_clk) begin
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#(clk_on) clk = 0;
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#(clk_off) clk = 1;
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end
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clk = 0;
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end
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end
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endmodule
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