29 lines
578 B
Coq
29 lines
578 B
Coq
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module tb;
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wire clk1;
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wire clk2;
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wire clk3;
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wire clk4;
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reg enable;
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reg [7:0] delay;
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clock_gen u0(enable, clk1);
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clock_gen #(.FREQ(100000)) u1(enable, clk2);
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clock_gen #(.FREQ(200000)) u2(enable, clk3);
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clock_gen #(.FREQ(400000)) u3(enable, clk4);
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integer i ;
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initial begin
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$dumpfile("test.lx2");
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$dumpvars(0,u1,u2,u3);
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enable <= 0;
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for ( i = 0; i < 10; i=i+1) begin
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delay = $random;
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#(delay) enable <= ~enable;
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$display("i=%0d delay=%0d", i, delay);
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#50;
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end
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#50 $finish;
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end
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endmodule
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