`include "proc_state_def.v"

module mux4 (in1,in2,in3,in4, sel,out); 
input [0:1] sel;
parameter WIDTH=16;
input [WIDTH-1:0] in1,in2,in3,in4;
output [WIDTH-1:0] out;
assign out = (sel == 'b00) ? in1 :
	(sel == 'b01) ? in2 :
	(sel == 'b10) ? in3 :
	in4;
endmodule

module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT);

/*** Global Definitions ***/
// State
reg [3:0] state;

// Registers
reg [19:0] ProgCount;
reg [15:0] CIR;
reg [15:0] PARAM1;
reg [15:0] PARAM2;
reg unaligned_access;

// Execution units
reg [1:0] in1_sel;
reg [1:0] in2_sel;
reg [1:0] out_sel;

/*** RESET LOGIC ***/
always @(negedge reset) begin
	if (reset==0) begin
		@(posedge clock);
		state=`PROC_HALT_STATE;
		ProgCount=0;//TODO: Reset Vector
		EXCEPTION=0;
		HALT=0;
		reg_read=1;
		reg_write=1;
		reg_read_read=1;
		unaligned_access=0;
		ALU_OUT=1;
		@(posedge reset)
		@(negedge clock);
		state=`PROC_IF_STATE_ENTRY;
	end
end

reg EXCEPTION;

/*** ALU and EXEC stage logic ***/

//Architectural Register file
reg [2:0] reg_addr;
reg [15:0] reg_data;
reg reg_read;
reg reg_write;
reg [2:0] reg_read_addr;
reg [15:0] reg_read_data;
reg reg_read_read;
wire [15:0] reg_data_;
assign reg_data_=reg_data;
register_file register_file(reg_addr,reg_data_,reg_read,reg_write,reg_read_addr,reg_read_data,reg_read_read);

//ALU
mux4 #(.WIDTH(16)) MUX16_1A(
	PARAM1,
	16'b0,
	16'b0,
	16'b0,
	in1_sel,
	ADDER16_1A);

mux4 #(.WIDTH(16)) MUX16_1B(
	PARAM2,
	reg_read_data,
	16'b0,
	16'b0,
	in2_sel,
	ADDER16_1B);

wire [15:0] ADDER16_1A;
wire [15:0] ADDER16_1B;
wire [15:0] ADDER16_1O;
wire ADDER16_1C;
reg ALU_OUT;
reg [15:0] temp_out;
ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,ALU_OUT,ADDER16_1O,ADDER16_1C);

/*** Processor stages ***/

`define invalid_instruction state=`PROC_IF_STATE_ENTRY;EXCEPTION=1;

always @(negedge clock) begin
	case(state)
		`PROC_IF_WRITE_CIR:begin
			if(unaligned_access)begin
				CIR[15:8] <= external_data_bus[7:0];
				ProgCount=ProgCount+1;
				state=`PROC_IF_STATE_EXTRA_FETCH_SET;
			end else begin
				CIR <= external_data_bus;
				state=`PROC_DE_STATE_ENTRY;
			end
		end
		`PROC_IF_STATE_EXTRA_FETCH:begin
				CIR[7:0] <= external_data_bus[15:8];
				state=`PROC_DE_STATE_ENTRY;
		end
		`PROC_EX_STATE_EXIT:begin
			case(out_sel)
				2'b11:begin
					reg_write=0;
					state=`PROC_IF_STATE_ENTRY;
				end
				default:begin
					`invalid_instruction
				end
			endcase
		end
		`PROC_DE_LOAD_16_EXTRA_FETCH_SET:begin
			external_address_bus = ProgCount;
			state=`PROC_DE_LOAD_16_EXTRA_FETCH;
		end
	endcase
end

always @(posedge clock) begin
	case(state)
		`PROC_HALT_STATE:begin
		end
		`PROC_IF_STATE_ENTRY:begin
			EXCEPTION=0;
			external_address_bus <= ProgCount;
			read <= 0;
			write <= 1;
			reg_read_read=1;
			reg_write=1;
			ALU_OUT=1;
			state=`PROC_IF_WRITE_CIR;
		end
		`PROC_IF_STATE_EXTRA_FETCH_SET:begin
			external_address_bus <= ProgCount;
			state=`PROC_IF_STATE_EXTRA_FETCH;
		end
		`PROC_DE_STATE_ENTRY:begin
			case(CIR[15:10])
				6'b000001 : begin
					/* ADD, ... */
					if ( CIR[9:9] == 0 )begin
						/* Add Immediate to accumulator */
						unaligned_access=~unaligned_access;
						in1_sel=2'b00;
						in2_sel=2'b01;
						out_sel=2'b11;
						reg_read_addr=3'b000;
						reg_addr=3'b000;
						reg_read_read=0;
						ALU_OUT=0;
						state=`PROC_DE_LOAD_16_PARAM;
					end else begin
						`invalid_instruction
					end
				end
				6'b100000 : begin
					/* ADD, ADC, SUB, SBB, CMP , AND, ... */
					case (CIR[5:3])
						3'b000 : begin
							/* Add Immediate to register/memory */
							if(unaligned_access==0)begin
								ProgCount=ProgCount+1;
								external_address_bus <= ProgCount;
							end
							in1_sel=2'b00;
							in2_sel=2'b01;
							out_sel=CIR[7:6];
							reg_read_addr=CIR[2:0];
							reg_addr=CIR[2:0];
							reg_read_read=0;
							ALU_OUT=0;
							state=`PROC_DE_LOAD_16_PARAM;
						end
						default:begin
							`invalid_instruction
						end
					endcase
				end
				6'b101100,
				6'b101101,
				6'b101110,
				6'b101111 : begin
					/*Move Immediate to register*/
					unaligned_access=~unaligned_access;
					in1_sel=2'b00;
					in2_sel=2'b00;
					out_sel=2'b11;
					reg_addr=CIR[10:8];
					ALU_OUT=0;
					PARAM2=0;
					state=`PROC_DE_LOAD_16_PARAM;
				end
				6'b111111 : begin
					/* INC */
					if (CIR[9:9] == 1 ) begin
						case (CIR[5:3])
							3'b000 :begin
								/* Increment Register or Memmory */
								if(unaligned_access==0)begin
									ProgCount=ProgCount+1;
									external_address_bus <= ProgCount;
								end
								in1_sel=2'b00;
								in2_sel=2'b01;
								out_sel=CIR[7:6];
								PARAM1=1;
								reg_read_addr=CIR[2:0];
								reg_addr=CIR[2:0];
								reg_read_read=0;
								ALU_OUT=0;
								state=`PROC_EX_STATE_ENTRY;
							end
							default:begin
								`invalid_instruction
							end
						endcase
					end else begin
						`invalid_instruction
					end
				end
				6'b111101 : begin
					/*HLT, CMC, TEST, NOT, NEG, MUL, IMUL, .... */
					case (CIR[9:8])
						2'b00:begin
							/* HLT*/
							unaligned_access=~unaligned_access;
							HALT=1;
							state=`PROC_HALT_STATE;
						end
						default:begin
							`invalid_instruction;
						end
					endcase

				end
				default:begin
					`invalid_instruction
				end
			endcase
		end
		`PROC_DE_LOAD_16_PARAM:begin
			if(unaligned_access==1)begin
				PARAM1[7:0] = external_data_bus[7:0];
				ProgCount=ProgCount+1;
				state=`PROC_DE_LOAD_16_EXTRA_FETCH_SET;
			end else begin
				PARAM1[7:0] = external_data_bus[15:8];
				PARAM1[15:8] = external_data_bus[7:0];
				ProgCount=ProgCount+1;
				state=`PROC_EX_STATE_ENTRY;
			end
		end
		`PROC_DE_LOAD_16_EXTRA_FETCH:begin
			PARAM1[15:8] = external_data_bus[15:8];
			state=`PROC_EX_STATE_ENTRY;
		end
		`PROC_EX_STATE_ENTRY:begin
			reg_data=ADDER16_1O;
			state=`PROC_EX_STATE_EXIT;
			EXCEPTION=0;
		end
	endcase
end


endmodule