/* processor.v - implementation of most functions of the 9086 processor

   This file is part of the 9086 project.

   Copyright (c) 2023 Efthymios Kritikos

   This program is free software: you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation, either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

`include "proc_state_def.v"
`include "alu_header.v"
`include "config.v"

module mux4 (in1,in2,in3,in4, sel,out); 
input [0:1] sel;
parameter WIDTH=16;
input [WIDTH-1:0] in1,in2,in3,in4;
output [WIDTH-1:0] out;
assign out = (sel == 'b00) ? in1 :
	(sel == 'b01) ? in2 :
	(sel == 'b10) ? in3 :
	in4;
endmodule

module processor ( input clock, input reset, output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT,output reg ERROR);

/*if we don't read, output the register to have the bus stable by the write falling edge*/
reg [15:0] data_bus_output_register;
assign external_data_bus=read?data_bus_output_register:'hz;

/*** Global Definitions ***/
// State
reg [`PROC_STATE_BITS-1:0] state;

// Registers
reg [19:0] ProgCount; /*TODO consider having single circuit to increment PC instead of having possible lots of adders all over the code*/
reg [15:0] CIR;
reg [15:0] PARAM1;
reg [15:0] PARAM2;
reg unaligned_access;
reg [1:0]MOD;
reg [2:0]RM;
reg Wbit;
reg [15:0]FLAGS;
/* . . . . O D I T S Z . A . P . C */
// C - Carry flag : carry out or borrow into the high order bit (8bit/16bit)
//
// P - Parity flag : is set if result has even parity
//
// A - Auxiliary flag : carry out from the low nibble to the high nibble or
// an equiv borrow. Used by decimal arithmetic instructions
//
// Z - Zero flag : Set when result of Operation is zero
//
// S - Sign flag : set if the high order bit of the result is 1. aka the sign
// of the result
//
// T - Trap flag : Set the CPU into single step mode where it generates an
// interrupt after each instruction
//
// I - Interrupt flag : 0: interrupts are masked
//
// D - Direction flag : 1: string instructions decrement 0: they increment
//
// O - Overflow flag : set on arithmetic overflow
reg [15:0] BYTE_WRITE_TEMP_REG;//we read 16bits here if we want to change just 8 and leave the rest


/*** RESET LOGIC ***/
always @(negedge reset) begin
	if (reset==0) begin
		@(posedge clock);
		state=`PROC_HALT_STATE;
		ProgCount=0;//TODO: Reset Vector
		HALT=0;
		reg_write_we=1;
		unaligned_access=0;
		ALU_1OE=1;
		@(posedge reset)
		@(negedge clock);
		state=`PROC_IF_STATE_ENTRY;
		MOD=2'b11;
		ERROR=0;
	end
end

/*** ALU and EXEC stage logic ***/

//Architectural Register file
reg [3:0] reg_write_addr;
wire [15:0] reg_write_data;
reg reg_write_we;
reg [3:0] reg_read_port1_addr;
reg [15:0] reg_read_port1_data;
reg [1:0] reg_write_in_sel;
mux4 #(.WIDTH(16)) REG_FILE_WRITE_IN_MUX(
	ALU_1O,
	16'hz,
	16'hz,
	16'hz,
	reg_write_in_sel,
	reg_write_data);
register_file register_file(reg_write_addr,reg_write_data,reg_write_we,reg_read_port1_addr,reg_read_port1_data);

/****   ALU 1  ******/
reg [1:0] in_alu1_sel1;
reg [1:0] in_alu1_sel2;
/* out_alu1_sel : { EXTRA_FUNCTIONS_BIT[0:0], MOD_OR_EXTRA_FUNCTION[1:0] } */
reg [2:0] out_alu1_sel;

mux4 #(.WIDTH(16)) MUX16_1A(
	PARAM1,
	reg_read_port1_data,
	{ProgCount[14:0],unaligned_access},
	16'b0,
	in_alu1_sel1,
	ALU_1A);

mux4 #(.WIDTH(16)) MUX16_1B(
	PARAM2,
	reg_read_port1_data,
	{ProgCount[14:0],unaligned_access},
	16'b0,
	in_alu1_sel2,
	ALU_1B);

wire [15:0] ALU_1A;
wire [15:0] ALU_1B;
wire [15:0] ALU_1O;
reg [`ALU_OP_BITS-1:0]ALU_1OP;
reg ALU_1OE;
wire [7:0] ALU_1FLAGS;
ALU ALU1(ALU_1A,ALU_1B,ALU_1OE,ALU_1O,ALU_1OP,ALU_1FLAGS,Wbit);

/*** Processor stages ***/

`define invalid_instruction state=`PROC_IF_STATE_ENTRY;ERROR=1;MOD=2'b11;
`define start_aligning_instruction if(unaligned_access==0)begin ProgCount=ProgCount+1; external_address_bus <= ProgCount; end /*we normally don't advance PC in case of singly byte unaligning instructions leaving us with two instructions in one read so do that here*/
`define start_unaligning_instruction unaligned_access=~unaligned_access;

always @(negedge clock) begin
	case(state)
		`PROC_IF_WRITE_CIR:begin
			if(unaligned_access)begin
				CIR[15:8] <= external_data_bus[7:0];
				ProgCount=ProgCount+1;
				state=`PROC_IF_STATE_EXTRA_FETCH_SET;
			end else begin
				CIR <= external_data_bus;
				state=`PROC_DE_STATE_ENTRY;
			end
		end
		`PROC_IF_STATE_EXTRA_FETCH:begin
			CIR[7:0] <= external_data_bus[15:8];
			state=`PROC_DE_STATE_ENTRY;
		end
		`PROC_EX_STATE_EXIT:begin
			case(out_alu1_sel) /*TODO: use RM*/
				3'b000,
					3'b001,
					3'b010 : begin
					case (RM) /* Duplicate code with write... */
						3'b000:begin
							/*[BX]+[SI]*/
							`invalid_instruction
						end
						3'b001:begin
							/*[BX]+[SI]*/
							`invalid_instruction
						end
						3'b010:begin
							/*[BP]+[SI]*/
							`invalid_instruction
						end
						3'b011:begin
							/*[BP]+[DI]*/
							`invalid_instruction
						end
						3'b100:begin
							/*[SI]*/
							reg_read_port1_addr=4'b1110;
							state=`PROC_MEMIO_WRITE;
						end
						3'b101:begin
							/*[DI]*/
							reg_read_port1_addr=4'b1111;
							state=`PROC_MEMIO_WRITE;
						end
						3'b110:begin
							/*d16 */
							`invalid_instruction
						end
						3'b111:begin
							/*[BX]*/
							reg_read_port1_addr=4'b1011;
							state=`PROC_MEMIO_WRITE;
						end
					endcase
				end
				3'b011:begin
					reg_write_we=0;
					state=`PROC_IF_STATE_ENTRY;
				end
				3'b101:begin
					ProgCount=ALU_1O[15:1];
					unaligned_access=ALU_1O[0:0];
					state=`PROC_IF_STATE_ENTRY;
				end
				3'b100:begin
					state=`PROC_IF_STATE_ENTRY;
				end
				default:begin
					`invalid_instruction
				end
			endcase
		end
		`PROC_DE_LOAD_16_EXTRA_FETCH_SET:begin
			external_address_bus = ProgCount;
			state=`PROC_DE_LOAD_16_EXTRA_FETCH;
		end
		`PROC_MEMIO_READ_SETADDR:begin
			external_address_bus = {1'b0,reg_read_port1_data[15:1]};
			state=reg_read_port1_data[0:0]?`PROC_MEMIO_GET_UNALIGNED_DATA:`PROC_MEMIO_GET_ALIGNED_DATA;
		end
		`PROC_MEMIO_PUT_BYTE:begin
			BYTE_WRITE_TEMP_REG=external_data_bus;
			state=`PROC_MEMIO_PUT_BYTE_STOP_READ;
		end
		`PROC_MEMIO_WRITE_EXIT:begin
			write=0;
			state=`PROC_IF_STATE_ENTRY;
		end
		`PROC_MEMIO_PUT_ALIGNED_DATA:begin
			read=1;
			data_bus_output_register={ALU_1O[7:0],ALU_1O[15:8]};
			state=`PROC_MEMIO_WRITE_EXIT;
		end
		`PROC_MEMIO_PUT_UNALIGNED_DATA:begin
			BYTE_WRITE_TEMP_REG=external_data_bus;
			state=`PROC_MEMIO_PUT_UNALIGNED_FIRST_BYTE;
		end
		`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT:begin
			write=0;
			state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT2;
			data_bus_output_register={BYTE_WRITE_TEMP_REG[15:8],ALU_1O[7:0]};
		end
		`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT3:begin
			BYTE_WRITE_TEMP_REG=external_data_bus;
			state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT4;
		end
	endcase
end

always @(posedge clock) begin
	case(state)
		`PROC_HALT_STATE:begin
		end
		`PROC_IF_STATE_ENTRY:begin
			`ifdef DEBUG_PC_ADDRESS
				/* Weird (possible bug) where even though the
				* testbench stop the clock after ERROR gets
				* raised the logic for the rising edge still
				* gets triggered printing this debug message. */
				if(ERROR!=1)
					$display("Fetched instruction at %04x",{ProgCount[18:0],unaligned_access});
			`endif
			external_address_bus <= ProgCount;
			read <= 0;
			write <= 1;
			reg_write_we=1;
			ALU_1OE=1;
			state=`PROC_IF_WRITE_CIR;
			reg_write_in_sel=2'b00;
		end
		`PROC_IF_STATE_EXTRA_FETCH_SET:begin
			external_address_bus <= ProgCount;
			state=`PROC_IF_STATE_EXTRA_FETCH;
		end
		/* 0 0 0 0  0 0 0 0 | 0 0 0 0  0 0 0 0 | 0 0 0 0  0 0 0 0 | 0 0 0 0  0 0 0 0 */
		/* AFTER THE IF STAGE WE HAVE THE FIRST BYTE OF THE
		* INSTRUCTION AND THE ONE FOLLOWING, ALIGNED CORRECTLY TO
		* CIR */
		`PROC_DE_STATE_ENTRY:begin
			case(CIR[15:10])
				6'b000001 : begin
					/* ADD, ... */
					if ( CIR[9:9] == 0 )begin
						/*       Add Immediate word/byte to accumulator           */
						/* 0 0 0 0  0 1 0 W |       DATA       |     DATA if W   |*/
						Wbit=CIR[8:8];
						if(Wbit)
							`start_unaligning_instruction
						else
							`start_aligning_instruction
						MOD=2'b11;
						in_alu1_sel1=2'b00;
						in_alu1_sel2=2'b01;
						out_alu1_sel=3'b011;
						reg_read_port1_addr={CIR[8:8],3'b000};
						reg_write_addr={CIR[8:8],3'b000};
						ALU_1OE=0;
						ALU_1OP=`ALU_OP_ADD;
						if(CIR[8:8]==1)
							state=`PROC_DE_LOAD_16_PARAM;
						else begin
							PARAM1[7:0]=CIR[7:0];
							state=`PROC_EX_STATE_ENTRY;
						end
					end else begin
						`invalid_instruction
					end
				end
				6'b100000 : begin
					/* ADD, ADC, SUB, SBB, CMP , AND, ... */
					case (CIR[5:3])
						3'b000 : begin
							/* Add Immediate word/byte to register/memory */
							/* 1 0 0 0  0 0 S W | MOD 0 0  0  R/M  |     < DISP LO >  |     < DISP HI >   |      DATA        |      DATA if W    |    */
							`start_aligning_instruction
							Wbit=CIR[8:8];
							MOD=2'b11;
							in_alu1_sel1=2'b00;
							in_alu1_sel2=2'b01;
							out_alu1_sel={1'b0,CIR[7:6]};
							reg_read_port1_addr={CIR[8:8],CIR[2:0]};
							reg_write_addr={CIR[8:8],CIR[2:0]};
							ALU_1OE=0;
							ALU_1OP=`ALU_OP_ADD;
							state=`PROC_DE_LOAD_16_PARAM;
							if(CIR[8:8]==1)
								state=`PROC_DE_LOAD_16_PARAM;
							else begin
								`invalid_instruction /*do 8bit loads*/
							end
						end
						default:begin
							`invalid_instruction
						end
					endcase
				end
				6'b101100,
					6'b101101:begin
					/*        MOV - Move Immediate byte to register            */
					/* 1 0 1 1  W  REG  |       DATA       |     DATA if W    |*/
					Wbit=CIR[11:11];
					if(Wbit)
						`start_unaligning_instruction
					else
						`start_aligning_instruction
					MOD=2'b11;
					in_alu1_sel1=2'b00;
					in_alu1_sel2=2'b00;
					out_alu1_sel=3'b011;
					reg_write_addr={1'b0,CIR[10:8]};
					PARAM1[7:0]=CIR[7:0];
					PARAM2=0;
					ALU_1OE=0;
					ALU_1OP=`ALU_OP_ADD;
					state=`PROC_EX_STATE_ENTRY;
				end
				6'b101110,
					6'b101111 : begin
					/*MOV - Move Immediate word to register*/
					Wbit=CIR[11:11];
					if(Wbit)
						`start_unaligning_instruction
					else
						`start_aligning_instruction
					MOD=2'b11;
					in_alu1_sel1=2'b00;
					in_alu1_sel2=2'b00;
					out_alu1_sel=3'b011;
					reg_write_addr={1'b1,CIR[10:8]};
					ALU_1OE=0;
					ALU_1OP=`ALU_OP_ADD;
					PARAM2=0;
					state=`PROC_DE_LOAD_16_PARAM;
				end

				6'b100010 : begin
					/*                      MOV - Reg/Mem to/from register                        */
					/* 1 0 0 0  1 0 D W | MOD   REG    RM  |    < DISP LO >   |    < DISP HI >   |*/
					`start_aligning_instruction
					MOD=CIR[7:6];
					RM=CIR[2:0];
					Wbit=CIR[8:8];
					in_alu1_sel2=2'b00;
					if(CIR[9:9] == 1)begin
						/* Mem/Reg to reg */
						if(MOD==2'b11)begin
							/*Reg to Reg*/
							in_alu1_sel1=2'b01;
							reg_read_port1_addr=CIR[2:0];
							state=`PROC_EX_STATE_ENTRY;
						end else begin
							/*Mem to Reg*/
							in_alu1_sel1=2'b00;
							state=`RPOC_MEMIO_READ;
						end
						out_alu1_sel=3'b011;
						reg_write_addr={Wbit,CIR[5:3]};
					end else begin
						/* Reg to Mem/Reg */
						if(MOD==2'b11)begin
							/*Reg to Reg*/
							in_alu1_sel1=2'b01;
							out_alu1_sel=3'b011;
							reg_write_addr={Wbit,CIR[2:0]};
							state=`PROC_EX_STATE_ENTRY;
						end else begin
							/*Reg to Mem*/
							in_alu1_sel1=2'b00;
							reg_read_port1_addr=CIR[5:3];
							out_alu1_sel={1'b0,MOD};
							state=`PROC_DE_LOAD_REG_TO_PARAM;
						end
						reg_read_port1_addr={Wbit,CIR[5:3]};
					end

					ALU_1OE=0;
					ALU_1OP=`ALU_OP_ADD;
					PARAM2=0;
				end
				6'b010000,//INC
				6'b010001,//INC
				6'b010010,//DEC
				6'b010011:begin//DEC
					/* DEC - Decrement Register */
					/*   | 0 1 0 0  1  REG  |   */
					/* INC - Increment Register */
					/*   | 0 1 0 0  0  REG  |   */
					`start_unaligning_instruction
					Wbit=1;
					in_alu1_sel1=2'b01;
					in_alu1_sel2=2'b00;
					out_alu1_sel=3'b011;
					MOD=2'b11;
					PARAM2=1;
					reg_read_port1_addr={1'b1,CIR[10:8]};
					reg_write_addr={1'b1,CIR[10:8]};
					ALU_1OE=0;
					if(CIR[11:11]==0)
						ALU_1OP=`ALU_OP_ADD;
					else
						ALU_1OP=`ALU_OP_SUB;
					state=`PROC_EX_STATE_ENTRY;
				end
				6'b111111 : begin
					/* INC */
					if (CIR[9:9] == 1 ) begin
						case (CIR[5:3])
							3'b000 :begin
								/*                          INC - Register/Memory                            */
								/* 1 1 1 1  1 1 1 W | MOD 0 0  0  R/M  |    < DISP LO>    |    < DISP HI>    */
								`start_aligning_instruction
								Wbit=CIR[8:8];
								MOD=CIR[7:6];
								RM=CIR[2:0];
								in_alu1_sel1=(MOD==2'b11)? 2'b01 : 2'b00;
								in_alu1_sel2=2'b00;/* number 1 */
								out_alu1_sel={1'b0,MOD};
								PARAM2=1;

								/*in case MOD=11 */
								reg_read_port1_addr={1'b0,RM};
								reg_write_addr={1'b0,RM};

								ALU_1OE=0;
								ALU_1OP=`ALU_OP_ADD;
								if ( CIR[7:6] == 2'b11 )
									state=`PROC_EX_STATE_ENTRY;
								else
									state=`RPOC_MEMIO_READ;
							end
							default:begin
								`invalid_instruction
							end
						endcase
					end else begin
						`invalid_instruction
					end
				end
				6'b111101 : begin
					/*HLT, CMC, TEST, NOT, NEG, MUL, IMUL, .... */
					case (CIR[9:8])
						2'b00:begin
							/*     HLT - Halt     */
							/* 1 1 1 1  0 1 0 0 | */
							`start_unaligning_instruction
							MOD=2'b11;
							HALT=1;
							state=`PROC_HALT_STATE;
						end
						default:begin
							`invalid_instruction;
						end
					endcase

				end
				6'b001111 : begin
					if ( CIR[9:9] == 0 ) begin
						/*         CMP - Compare Immediate with accumulator        */
						/* 0 0 1 1  1 1 0 W |       DATA       |     DATA if W    |*/
						/*                                                         */
						/* NOTE: 8086 doc doesn't show the third byte but the      */
						/* W flag and my assembler seem to disagree                */
						Wbit=CIR[8:8];
						if(Wbit)
							`start_unaligning_instruction
						else
							`start_aligning_instruction
						MOD=2'b11;
						in_alu1_sel1=2'b00;
						in_alu1_sel2=2'b01;
						reg_read_port1_addr={CIR[8:8],3'b000};
						out_alu1_sel=3'b100;
						ALU_1OE=0;
						ALU_1OP=`ALU_OP_SUB;
						if(CIR[8:8]==1)
							state=`PROC_DE_LOAD_16_PARAM;
						else begin
							PARAM1[7:0]=CIR[7:0];
							state=`PROC_EX_STATE_ENTRY;
						end
					end else begin
						`invalid_instruction
					end
				end
				6'b011100,
					6'b011101,
					6'b011110,
					6'b011111:begin
					/*     Conditional relative jumps       */
					/*        JE/JZ - Jump on Zero          */
					/* 0 1 1 1  0 1 0 0 |     IP-INC8      |*/
					/*         JS - Jump on Sign            */
					/* 0 1 1 1  1 0 0 0 |     IP-INC8      |*/
					/*       JNS -Jump on not Sign          */
					/* 0 1 1 1  1 0 0 1 |     IP-INC8      |*/
					/*                ....                  */
					`start_aligning_instruction
					Wbit=1;
					in_alu1_sel1=2'b10;
					in_alu1_sel2=2'b00;
					PARAM2={{8{CIR[7:7]}},CIR[7:0]};
					ALU_1OE=0;
					ALU_1OP=`ALU_OP_ADD_SIGNED_B;
					out_alu1_sel=3'b101;
					case(CIR[11:9])
						4'b000: begin
							/* Jump on (not) Overflow */
							if(FLAGS[11:11]==CIR[8:8])
								state=`PROC_IF_STATE_ENTRY;
							else begin
								state=`PROC_EX_STATE_ENTRY;
							end
						end
						4'b010: begin
							/* Jump on (not) Zero */
							if(FLAGS[6:6]==CIR[8:8])
								state=`PROC_IF_STATE_ENTRY;
							else
								state=`PROC_EX_STATE_ENTRY;
						end
						4'b100: begin
							/* Jump on (not) Sign */
							if(FLAGS[7:7]==CIR[8:8])
								state=`PROC_IF_STATE_ENTRY;
							else
								state=`PROC_EX_STATE_ENTRY;
						end
						4'b101: begin
							/* Jump on (not) Parity */
							if(FLAGS[2:2]==CIR[8:8])
								state=`PROC_IF_STATE_ENTRY;
							else
								state=`PROC_EX_STATE_ENTRY;
						end
						default:begin
							`invalid_instruction; /*We don't support that condition*/
						end
					endcase
				end
				6'b111010:begin
					/* JMP,CALL */
					case(CIR[9:8])
						2'b00: begin
							/*            CALL - Call direct within segment            */
							/* 1 1 1 0  1 0 0 0 |     IP-INC-LO    |     IP-INC-HI    |*/
							`invalid_instruction
						end
						2'b01: begin
							/*     JMP - Uncoditional Jump direct within segment       */
							/* 1 1 1 0  1 0 0 1 |     IP-INC-LO    |     IP-INC-HI    |*/
							`invalid_instruction
						end
						2'b10: begin
							/*                          JMP - Unconditional jump direct intersegment                         */
							/* 0 0 0 0  0 0 0 0 |       IP-LO      |       IP-HI      |       CS-LO      |      CS-HI      | */
							`invalid_instruction
						end
						2'b11: begin
							/* JMP - Unconditional jump direct within segment (short) */
							/*        | 1 1 1 0  1 0 0 1 |     IP-INC-LO    |         */
							`start_aligning_instruction
							Wbit=1;
							in_alu1_sel1=2'b10;
							in_alu1_sel2=2'b00;
							PARAM2={{8{CIR[7:7]}},CIR[7:0]};
							ALU_1OE=0;
							ALU_1OP=`ALU_OP_ADD_SIGNED_B;
							out_alu1_sel=3'b101;
							state=`PROC_EX_STATE_ENTRY;
						end
					endcase
				end
				default:begin
					`invalid_instruction
				end
			endcase
		end
		`PROC_DE_LOAD_REG_TO_PARAM:begin
			PARAM1=reg_read_port1_data;
			state=`PROC_EX_STATE_ENTRY;
		end
		`PROC_DE_LOAD_16_PARAM:begin
			if(unaligned_access==1)begin
				PARAM1[7:0] = external_data_bus[7:0];
				ProgCount=ProgCount+1;
				state=`PROC_DE_LOAD_16_EXTRA_FETCH_SET;
			end else begin
				PARAM1[7:0] = external_data_bus[15:8];
				PARAM1[15:8] = external_data_bus[7:0];
				ProgCount=ProgCount+1;
				state=`PROC_EX_STATE_ENTRY;
			end
		end
		`PROC_DE_LOAD_16_EXTRA_FETCH:begin
			PARAM1[15:8] = external_data_bus[15:8];
			state=`PROC_EX_STATE_ENTRY;
		end
		`RPOC_MEMIO_READ:begin
			/*Decode MOD R/M, read the data and place it to PARAM1*/
			case (RM)
				3'b000:begin
					/*[BX]+[SI]*/
					`invalid_instruction
				end
				3'b001:begin
					/*[BX]+[SI]*/
					`invalid_instruction
				end
				3'b010:begin
					/*[BP]+[SI]*/
					`invalid_instruction
				end
				3'b011:begin
					/*[BP]+[DI]*/
					`invalid_instruction
				end
				3'b100:begin
					/*[SI]*/
					reg_read_port1_addr=4'b1110;
					state=`PROC_MEMIO_READ_SETADDR;
				end
				3'b101:begin
					/*[DI]*/
					reg_read_port1_addr=4'b1111;
					state=`PROC_MEMIO_READ_SETADDR;
				end
				3'b110:begin
					/*d16 */
					`invalid_instruction
				end
				3'b111:begin
					/*[BX]*/
					reg_read_port1_addr=4'b1011;
					state=`PROC_MEMIO_READ_SETADDR;
				end
			endcase
			if(MOD!=2'b00)begin
				/*Actually check if 01 and add the 8bits or if 10 add the 16bits ....*/
				`invalid_instruction;
			end

		end
		`PROC_MEMIO_GET_ALIGNED_DATA:begin
			PARAM1=(Wbit==1)? external_data_bus : {8'b00000000,external_data_bus[15:8]} ;
			state=`PROC_EX_STATE_ENTRY;
		end
		`PROC_MEMIO_GET_UNALIGNED_DATA:begin
			if(Wbit==1) begin
				`invalid_instruction //easy to implement, get the other byte from the next address
			end else begin
				PARAM1={8'b00000000,external_data_bus[7:0]};
				state=`PROC_EX_STATE_ENTRY;
			end
		end
		`PROC_EX_STATE_ENTRY:begin
			FLAGS[7:0] = ALU_1FLAGS[7:0];
			state=`PROC_EX_STATE_EXIT;
		end
		`PROC_MEMIO_WRITE:begin
			/* ADDRESS: reg_read_port1_data   DATA:ALU1_O */
			$display("Writing at %04x , %04x",reg_read_port1_data,ALU_1O);
			external_address_bus = {1'b0,reg_read_port1_data[15:1]};
			state = (Wbit==0) ? `PROC_MEMIO_PUT_BYTE : (reg_read_port1_data[0:0]?`PROC_MEMIO_PUT_UNALIGNED_DATA:`PROC_MEMIO_PUT_ALIGNED_DATA) ;
		end
		`PROC_MEMIO_PUT_BYTE_STOP_READ:begin
			read=1;
			state=`PROC_MEMIO_WRITE_EXIT;
			if(reg_read_port1_data[0:0]==0)
				data_bus_output_register={ALU_1O[7:0],BYTE_WRITE_TEMP_REG[7:0]};
			else
				data_bus_output_register={BYTE_WRITE_TEMP_REG[15:8],ALU_1O[7:0]};
		end
		`PROC_MEMIO_PUT_UNALIGNED_FIRST_BYTE:begin
			read=1;
			state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT;
			data_bus_output_register={BYTE_WRITE_TEMP_REG[15:8],ALU_1O[7:0]};
		end
		`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT2:begin
			external_address_bus=external_address_bus+1;
			write=1;
			read=0;
			state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT3;
		end
		`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT4:begin
			read=1;
			state=`PROC_MEMIO_WRITE_EXIT;
			data_bus_output_register={ALU_1O[15:8],BYTE_WRITE_TEMP_REG[7:0]};
		end
	endcase
end


endmodule