/* registers.v - implementation of the architectural register file for the 9086 CPU

   This file is part of the 9086 project.

   Copyright (c) 2023 Efthymios Kritikos

   This program is free software: you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation, either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

`include "config.v"

/* Register address format:
* [W-bit] [ 3-bit address] */
module register_file (write_port1_addr,write_port1_data,write_port1_we,read_port1_addr,read_port1_data);
input [3:0] write_port1_addr,read_port1_addr;
input [15:0]  write_port1_data;
output [15:0] read_port1_data;
input write_port1_we;

reg [15:0] registers [7:0];

assign read_port1_data = ( read_port1_addr[3:3] ? registers[read_port1_addr[2:0]] :
	( read_port1_addr[2:2] ? {8'b0,registers[read_port1_addr[2:0]][15:8]} : {8'b0,registers[read_port1_addr[2:0]][7:0]} ) );

`ifdef DEBUG_REG_WRITES
	string debug_name;
`endif

always @(negedge write_port1_we) begin
	if(write_port1_addr[3:3]==1)begin
		/* Word  : AX,CX,DX,BX,SP,BP,SI,DI */
		registers[write_port1_addr[2:0]]=write_port1_data;
	end else begin
		/* Byte  : AL,CL,DL,BL,AX,CX,DX,BX */
		if(write_port1_addr[2:2]==1)begin
			/* Byte */
			registers[write_port1_addr[2:0]][15:8]=write_port1_data[7:0];
		end else begin
			/* Byte */
			registers[write_port1_addr[2:0]][7:0]=write_port1_data[7:0];
		end
	end

	`ifdef DEBUG_REG_WRITES
		if(write_port1_addr[3:2]==2'b11)begin
			case(write_port1_addr[1:0])
				2'b00: debug_name="sp";
				2'b01: debug_name="bp";
				2'b10: debug_name="si";
				2'b11: debug_name="di";
			endcase
		end else begin
			case(write_port1_addr[1:0])
				2'b00: debug_name="ax";
				2'b01: debug_name="cx";
				2'b10: debug_name="dx";
				2'b11: debug_name="bx";
			endcase
		end

		$display("register %%%s update to $0x%04x",debug_name,registers[write_port1_addr[2:0]]);
	`endif
end
endmodule