#   This file is part of the 9086 project.
#
#   Copyright (c) 2023 Efthymios Kritikos
#
#   This program is free software: you can redistribute it and/or modify
#   it under the terms of the GNU General Public License as published by
#   the Free Software Foundation, either version 3 of the License, or
#   (at your option) any later version.
#
#   This program is distributed in the hope that it will be useful,
#   but WITHOUT ANY WARRANTY; without even the implied warranty of
#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
#   GNU General Public License for more details.
#
#   You should have received a copy of the GNU General Public License
#   along with this program.  If not, see <http://www.gnu.org/licenses/>.
#
TOP_LEVEL_SOURCE=system.v #TODO I really don't like this variable and its name
SOURCES=processor.v memory.v registers.v alu.v decoder.v general.v biu.v execute.v
EVENT_SIM_TESTBENCH=testbench.v
VERILATOR_TESTBENCH=testbench.cpp
INCLUDES=exec_state_def.v alu_header.v config.v ucode_header.v error_header.v
SYSTEM_VVP=system.vvp
VERILATOR_BIN=obj_dir/Vsystem
BOOT_CODE=boot_code.txt
GTKWSAVE=../gtkwave_savefile.gtkw
MICROCODE=ucode.txt

NO_ASM=0
include ../common.mk

#build options
VERILATOR_OPTS += --cc --exe

#binary options
VERILATOR_OPTS += --trace-fst --threads 1 --autoflush

#linter options
VERILATOR_OPTS += -Wall --Wno-DECLFILENAME

#optimisation options
VERILATOR_OPTS += -x-assign fast --x-initial fast
#For testing use:
#VERILATOR_OPTS += -x-assign unique --x-initial unique

# COMPILING
${SYSTEM_VVP} : ${TOP_LEVEL_SOURCE} ${SOURCES} ${INCLUDES} ${EVENT_SIM_TESTBENCH}
	${QUIET_IVERILOG}
	${Q}iverilog -g2012 -D CALCULATE_IPC -D OUTPUT_JSON_STATISTICS -o "$@" ${TOP_LEVEL_SOURCE} ${SOURCES} ${EVENT_SIM_TESTBENCH}

${VERILATOR_BIN}: ${VERILATOR_BIN}.mk
	${Q}make ${MAKEOPTS} OPT_FAST="-O2 -march=native -mtune=native" -C obj_dir -f ../verilator_makefile Vsystem

${VERILATOR_BIN}.mk: ${VERILATOR_TESTBENCH} ${TOP_LEVEL_SOURCE} ${SOURCES} ${INCLUDES}
	${QUIET_VERILATOR}
	${Q}verilator -DCALCULATE_IPC -DOUTPUT_JSON_STATISTICS ${VERILATOR_OPTS} $^

include fpga_config/${FPGA_BOARD}/config.mk

# Synthesis and bitstream creation for ECP5
ifeq "${ECP5_DEVICE}" "25F"
NEXTPNR_ECP5_DEV=--25k
else ifeq "${ECP5_DEVICE}" "85F"
NEXTPNR_ECP5_DEV=--85k
else
$(error invalid ECP5 device ${ECP5_DEVICE})
endif

ECP5_TARGETS=synth_ecp5.json synth_ecp5_out.config synth_ecp5.bit synth_ecp5.dfu synth_pnr_report.json
ECP5_TARGETS+=abc.history # created from yosys

EXTRA_SYNTHESIS_SOURCES=peripherals/I2C_driver.v peripherals/ascii_to_HD44780_driver.v peripherals/pcf8574_for_HD44780.v peripherals/Wishbone_IO_driver.v peripherals/Wishbone_memory_driver.v
EXTERNAL_IP_SOURCES=external_ip/litedram_core_ecp5_phy.v

simplified_ucode.txt:ucode.txt
	${Q}tr 'x' '0' < $^ | sed 's@//.*@@' | grep ^@ |sort | sed 's/.* .//;s/ $$//' | tr -d _ > $@

#TODO: we are relying on yosys to trim the input program txt file and hope its enough for the whole program...
synth_ecp5.json: ${SOURCES} fpga_config/${FPGA_BOARD}/fpga_top.v ${EXTRA_SYNTHESIS_SOURCES} ${EXTERNAL_IP_SOURCES} ${INCLUDES} ../boot_code/bios.stxt simplified_ucode.txt
	${QUIET_YOSYS}
	${Q} yosys -q -p 'read_verilog -defer -noautowire -sv '"${SOURCES} fpga_config/${FPGA_BOARD}/fpga_top.v ${EXTRA_SYNTHESIS_SOURCES} ${EXTERNAL_IP_SOURCES}; attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0; synth_ecp5 -json $@ -abc9 -top fpga_top"

NEXTPNR_SEED ::= $(shell seq 1 200|sort -R|head -n1)

synth_ecp5_out.config:synth_ecp5.json
	${QUIET_NEXTPNR}
	${Q}printf '\e[1;30mNotice: nextpnr rng seed is : %s\e[0m\n' "${NEXTPNR_SEED}"
	${Q} nextpnr-ecp5 --threads 5 --timing-allow-fail --seed ${NEXTPNR_SEED} --Werror -q --json $< --textcfg $@.1 ${NEXTPNR_ECP5_DEV} --package ${ECP5_PACKAGE} --speed 8 --lpf fpga_config/${FPGA_BOARD}/pin_constraint.pcf --report=synth_pnr_report.json
	${Q}../tools/parse_nextpnr_stats.sh --brief synth_pnr_report.json
	${Q}mv "$@.1" "$@"

synth_ecp5.bit:synth_ecp5_out.config
	${QUIET_ECPPACK}
	${Q}ecppack --compress --freq 38.8 --input $< --bit $@

synth_ecp5.dfu:synth_ecp5.bit
	${QUIET_DFU_SUFFIX}
	${Q}cp "$<" synth_ecp5.temp_dfu
	@#From some testing, dfu-suffix does output errors to stderr so this should be fine
	${Q}dfu-suffix --vid 1209 --pid 5af0 --add synth_ecp5.temp_dfu > /dev/null
	${Q}mv synth_ecp5.temp_dfu "$@"

upload_orangecrab:synth_ecp5.dfu
	${QUIET_DFU_UTIL}
	${Q}stdbuf -o0 dfu-util --download "$<" |stdbuf -o0 tr '\n' '\a' | stdbuf -o0 tr '\r' '\n' | grep Download --line-buffered | stdbuf -o0 tr '\n' '\r' |stdbuf -o0 tr '\a' '\n'

nextpnr-gui: synth_ecp5.json
	${QUIET_NEXTPNR}
	${Q} nextpnr-ecp5 --seed ${NEXTPNR_SEED} --json $< ${NEXTPNR_ECP5_DEV} --package ${ECP5_PACKAGE} --speed 8 --lpf fpga_config/${FPGA_BOARD}/pin_constraint.pcf --gui

external_ip/litedram_core_ecp5_phy.v:
	${QUIET_DOWNLOAD}
	${Q}../tools/gen_litedram.sh -q "$@"

upload: upload_orangecrab

.PHONY: clean
clean:
	$(call QUIET_CLEAN,system)
	${Q}rm -rf ${SYSTEM_VVP} *.fst boot_code.txt boot_code.bin *memdump *memdumptxt obj_dir *json simplified_ucode.txt ${ECP5_TARGETS}