`include "alu_header.v"

module ALU(input [15:0]A,input [15:0]B, input oe,output reg [15:0]OUT,input [`ALU_OP_BITS-1:0]op,output wire [7:0]FLAGS,input Wbit);
reg C_FLAG;

assign FLAGS={(Wbit==1)?OUT[15:15]:OUT[7:7],(Wbit==1) ? (OUT[15:0]=='h0000) : (OUT[7:0]=='h00),5'b00000,C_FLAG};

always @ ( * ) begin
	case (op)
		`ALU_OP_ADD: {C_FLAG,OUT}=A+B;
		`ALU_OP_SUB: {C_FLAG,OUT}=A-B;
		`ALU_OP_AND: OUT=A&B;
		`ALU_OP_OR:  OUT=A|B;
		`ALU_OP_XOR: OUT=A^B;
	endcase
end

endmodule