`timescale 1ns/1ps
`include "proc_state_def.v"

module clock_gen (input enable, output reg clk);

parameter FREQ = 1000;  // in HZ
parameter PHASE = 0;    // in degrees
parameter DUTY = 50;    // in percentage 

real clk_pd	= 1.0/FREQ * 1000000; 	// convert to ms
real clk_on	= DUTY/100.0 * clk_pd;
real clk_off	= (100.0 - DUTY)/100.0 * clk_pd;
real quarter	= clk_pd/4;
real start_dly	= quarter * PHASE/90;

reg start_clk;

initial begin
end

// Initialize variables to zero
initial begin
	clk <= 0;
	start_clk <= 0;
end

// When clock is enabled, delay driving the clock to one in order
// to achieve the phase effect. start_dly is configured to the 
// correct delay for the configured phase. When enable is 0,
// allow enough time to complete the current clock period
always @ (posedge enable or negedge enable) begin
	if (enable) begin
		#(start_dly) start_clk = 1;
	end else begin
		#(start_dly) start_clk = 0;
	end      
end

// Achieve duty cycle by a skewed clock on/off time and let this
// run as long as the clocks are turned on.
always @(posedge start_clk) begin
	if (start_clk) begin
		clk = 1;

		while (start_clk) begin
			#(clk_on)  clk = 0;
			#(clk_off) clk = 1;
		end

		clk = 0;
	end
end 
endmodule


module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT);
/* State */
reg [3:0] state;
reg instruction_finished;

/* Registers */
reg [19:0] ProgCount;
reg [15:0] CIR;
reg [15:0] PARAM1;
reg [15:0] PARAM2;

/* RESET LOGIC */
always @(negedge reset) begin
	if (reset==0) begin
		@(posedge clock);
		ProgCount=0;//TODO: Reset Vector
		ADD_INST=0;
		EXCEPTION=0;
		INC_INST=0;
		HALT=0;
		@(negedge clock);
		@(posedge clock);
		state=`PROC_IF_STATE_ENTRY;
	end
end

/* Processor stages */
reg ADD_INST,EXCEPTION,INC_INST;

always @(negedge clock) begin
	case(state)
		`PROC_IF_WRITE_CIR:begin
			CIR <= external_data_bus;
			ProgCount=ProgCount+1;
			state=`PROC_DE_STATE_ENTRY;
		end
	endcase
end

always @(posedge clock) begin
	case(state)
		`PROC_HALT_STATE:
			HALT=1;
		`PROC_IF_STATE_ENTRY:begin
			external_address_bus <= ProgCount;
			read <= 0;
			write <= 1;
			state=`PROC_IF_WRITE_CIR;
		end
		`PROC_DE_STATE_ENTRY:begin
			external_address_bus <= ProgCount; /*Remenance from IF*/
			case(CIR[15:10])
				6'b100000 : begin
					case (CIR[5:3])
						3'b000 :begin
							ADD_INST=1;
							state=`PROC_DE_LOAD_16_PARAM;
						end
						default:begin
							EXCEPTION=1;
							state=`PROC_EX_STATE_ENTRY;
						end
					endcase
				end
				6'b111111 : begin
					if (CIR[9:9] == 1 ) begin
						case (CIR[5:3])
							3'b000 :begin
								INC_INST=1;
								state=`PROC_EX_STATE_ENTRY;
							end
							default:begin
								EXCEPTION=1;
								state=`PROC_EX_STATE_ENTRY;
							end
						endcase
					end else begin
						EXCEPTION=1;
						state=`PROC_EX_STATE_ENTRY;
					end
				end
				default:begin
					EXCEPTION=1;
					state=`PROC_EX_STATE_ENTRY;
				end
			endcase
		end
		`PROC_DE_LOAD_16_PARAM:begin
			PARAM1 <= external_data_bus;
			ProgCount=ProgCount+1;
			state=`PROC_EX_STATE_ENTRY;
		end
		`PROC_EX_STATE_ENTRY:begin
			EXCEPTION=0;ADD_INST=0;INC_INST=0;
			state=`PROC_IF_STATE_ENTRY;
		end
	endcase
end

endmodule