/* system.v - A basic test system with memory and IO for the 9086 CPU This file is part of the 9086 project. Copyright (c) 2023 Efthymios Kritikos This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . */ `timescale 1ns/1ps module system ( input clock,input reset, output [19:0]address_bus, inout [15:0]data_bus,output BHE, output rd, output wr, output IOMEM, output HALT, output ERROR); processor p(clock,reset,address_bus,data_bus,rd,wr,BHE,IOMEM,HALT,ERROR); doublemem sysmem(address_bus,data_bus,rd,wr,BHE,IOMEM); string waveform_name; initial begin if($value$plusargs("WAVEFORM=%s",waveform_name))begin $dumpfile(waveform_name); $dumpvars(0,p); end end always @(negedge wr) begin if(IOMEM==1'b1 && address_bus[7:0]==8'hA5 ) $write("%s" ,data_bus[15:8]); //if(CIR[7:0]==8'h21 && register_file.registers[0][15:8]==8'h02)begin // $write("%s" ,register_file.registers[2][7:0]); //end end reg [1:0] finish; string memdump_name; always @(posedge HALT) begin $display("Processor halted.\nCycles run for: %d",cycles-1); if($value$plusargs("MEMDUMP=%s",memdump_name))begin $writememh(memdump_name, sysmem.memory,0,32767); end finish<=2'd1; end always @(posedge clock) begin /* Allow some clock cycles for the waveform*/ case(finish) 2'd0: begin end 2'd1: finish <= 2; 2'd2: finish <= 3; 2'd3: $finish; endcase end always @(posedge ERROR) begin $display("PROCESSOR RUN INTO AN ERROR.\nCycles run for: %d",cycles-1); if($value$plusargs("MEMDUMP=%s",memdump_name))begin $writememh(memdump_name, system.sysmem.memory,0,32767); end finish<=2'd1; end integer cycles=0; always @(posedge clock)begin if(reset==1) cycles<=cycles+1; else cycles<=0; end endmodule