/* Register address fromat:
* [W-bit] [ 3-bit address] */
module register_file (write_port1_addr,write_port1_data,write_port1_we,read_port1_addr,read_port1_data,read_port1_oe);
input [3:0] write_port1_addr,read_port1_addr;
input [15:0]  write_port1_data;
output [15:0] read_port1_data;
input read_port1_oe;
input write_port1_we;

reg [15:0] registers [7:0];

assign read_port1_data = !read_port1_oe ?
	( read_port1_addr[3:3] ? registers[read_port1_addr[2:0]] :
	( read_port1_addr[2:2] ? {8'b0,registers[read_port1_addr[2:0]][15:8]} : {8'b0,registers[read_port1_addr[2:0]][7:0]} ) ) : 'hz;

`define DEBUG_REG_WRITES

`ifdef DEBUG_REG_WRITES
	string debug_name;
	logic[15:0] debug_value;
`endif

always @(negedge write_port1_we) begin
	if(write_port1_addr[3:3]==1)begin
		/* Word  : AX,CX,DX,BX,SP,BP,SI,DI */
		registers[write_port1_addr[2:0]]=write_port1_data;
	end else begin
		/* Byte  : AL,CL,DL,BL,AX,CX,DX,BX */
		if(write_port1_addr[2:2]==1)begin
			/* Byte */
			registers[write_port1_addr[2:0]][15:8]=write_port1_data[7:0];
		end else begin
			/* Byte */
			registers[write_port1_addr[2:0]][7:0]=write_port1_data[7:0];
		end
	end

	`ifdef DEBUG_REG_WRITES
		if(write_port1_addr[3:2]==2'b11)begin
			case(write_port1_addr[1:0])
				2'b00: debug_name="sp";
				2'b01: debug_name="bp";
				2'b10: debug_name="si";
				2'b11: debug_name="di";
			endcase
			debug_value=registers[write_port1_addr[2:0]];
		end else begin
			case(write_port1_addr[1:0])
				2'b00: debug_name="ax";
				2'b01: debug_name="cx";
				2'b10: debug_name="dx";
				2'b11: debug_name="bx";
			endcase
			debug_value=registers[write_port1_addr[2:0]];
		end


		$display("register %%%s update to $0x%04x",debug_name,debug_value);
	`endif
end
endmodule