module tb;
  wire clock;
  reg reset;
  reg  clk_enable;

  processor p(clock,reset);
  
  clock_gen #(.FREQ(1000)) u1(clk_enable, clock);

  initial begin
    $dumpfile("test.lx2");
    $dumpvars(0,p);
    clk_enable <= 1;

    #($random%500)
    reset = 0;
    #(100) 
    reset = 1;
    #(10000)

    #50 $finish;
  end
endmodule