#### ECP5 specific ####
ECP5_DEVICE=25F
# ECP5_DEVICE: 25F: Create bitstream for the LFE5U-25F
#              85F: Create bitstream for the LFE5U-85F
ECP5_PACKAGE=CSFBGA285
# ECP5_PACKAGE: CSFBGA285: The one used in OrangeCrab

FPGA_FILE_EXT=dfu

#This is on the 8th postiion in the chip id, for example
# LFE5U-25-7BG381I
#          ^---------- this would be a 7 speed grade
#
# 6 is the slowest and 8 is the fastest
ECP5_SPEED_GRADE=8

ROM_PART_ID=24lc512

########   End of user configuration   ########

#NOT USED OUTSIDE OF HERE
FPGA_SOC_COMMON_SOURCES=peripherals/I2C_driver.v peripherals/ascii_to_HD44780_driver.v peripherals/pcf8574_for_HD44780.v peripherals/Wishbone_IO_driver.v peripherals/Wishbone_memory_driver.v peripherals/I2C_driver_multiplexer.v peripherals/CPU_to_I2C_driver_bridge.v

FPGA_SOC_SOURCES=${FPGA_SOC_COMMON_SOURCES} external_ip/litedram_core_ecp5_phy.v
FPGA_SOC_SIM_SOURCES=${FPGA_SOC_COMMON_SOURCES} fpga_config/OrangeCrab_r0.2.1/verilator_config.vlt external_ip/litedram_core_ecp5_phy_sim.v

FPGA_BOOTCODE=../boot_code/i2c_bootloader.stxt

ROM_FILE=../boot_code/brainfuck_mandelbrot.bin

upload_bitstream: dfu_upload
upload_bootrom: minipro_upload

${BUILD_FILES_PREFIX}bitstream_${BUILD_NAME}.bit:${BUILD_FILES_PREFIX}nextpnr-ecp5_${BUILD_NAME}.bit
	${Q}cp "$^" "$@"

${BUILD_FILES_PREFIX}synth_${FPGA_BOARD}.json:${BUILD_FILES_PREFIX}synth_ecp5_${FPGA_BOARD}.json
	${Q}cp "$^" "$@"