/* decoder.v - Implementation of instruction opcode decoding logic
This file is part of the 9086 project.
Copyright (c) 2023 Efthymios Kritikos
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see . */
`include "proc_state_def.v"
`include "alu_header.v"
`include "ucode_header.v"
module microcode(
input [`UCODE_ADDR_BITS-1:0] ADDR,
output [`UCODE_DATA_BITS-1:0] DATA
);
initial begin
string ucode_path;
if($value$plusargs("MICROCODE=%s",ucode_path))begin
$readmemb(ucode_path,ucode,0,`UCODE_SIZE-1);
end else begin
$display("Please supply microcode rom file as a runtime vvp argument +MICROCODE=");
$finish;
end
end
reg [`UCODE_DATA_BITS-1:0] ucode [ 0:`UCODE_SIZE-1 ];
assign DATA=ucode[ADDR];
endmodule
module decoder(
input wire [15:0] CIR,input wire [15:0] FLAGS, output wire [4:0] INSTRUCTION_INFO, output wire [1:0]DECODER_SIGNALS,output reg [`PROC_STATE_BITS-1:0]next_state
,output reg [1:0]MOD, output reg [2:0]RM, output reg [15:0] PARAM1,output reg [15:0] PARAM2
,output reg [1:0]in_alu1_sel1,output reg [1:0]in_alu1_sel2,output reg [2:0]out_alu1_sel
,output wire [11:0]REGISTER_FILE_CONTROL
,output reg [2:0]ALU_1OP
,output reg [`UCODE_ADDR_BITS-1:0] seq_addr_entry, input wire SIMPLE_MICRO, input wire [`UCODE_ADDR_BITS-1:0] seq_addr_input
);
reg [3:0]reg_read_port1_addr;
reg [3:0]reg_read_port2_addr;
reg [3:0]reg_write_addr;
assign REGISTER_FILE_CONTROL={reg_write_addr,reg_read_port1_addr,reg_read_port2_addr};
/* For correct fetching of instructions and global options for the alu */
reg Wbit,Sbit,unaligning,opcode_size,has_operands;
assign INSTRUCTION_INFO={Wbit,Sbit,unaligning,opcode_size,has_operands};
reg ERROR, HALT;
assign DECODER_SIGNALS={ERROR,HALT};
wire [`UCODE_DATA_BITS-1:0] ucode_data;
reg [`UCODE_ADDR_BITS-1:0] UCODE_ADDR;
microcode ucode(seq_addr_input,ucode_data);
/* 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 */
`define invalid_instruction next_state=`PROC_IF_STATE_ENTRY;ERROR=1;MOD=2'b11;
`define start_aligning_instruction unaligning=0;
`define start_unaligning_instruction unaligning=1;
always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
if (SIMPLE_MICRO==0)begin
ERROR=0;HALT=0;
casex({CIR[15:8],CIR[5:3]})
11'b0000_010x_xxx : begin
/* Add Immediate word/byte to accumulator */
/* 0 0 0 0 0 1 0 W | DATA | DATA if W |*/
seq_addr_entry=`UCODE_NO_INSTRUCTION;
opcode_size=0;
has_operands=1;
Wbit=CIR[8:8];
if(Wbit)
`start_unaligning_instruction
else
`start_aligning_instruction
MOD=2'b11;
in_alu1_sel1=2'b00;
in_alu1_sel2=2'b01;
out_alu1_sel=3'b011;
reg_read_port2_addr={Wbit,3'b000};
reg_write_addr={Wbit,3'b000};
ALU_1OP=`ALU_OP_ADD;
if(Wbit==1)
next_state=`PROC_DE_LOAD_16_PARAM;
else begin
PARAM1[7:0]=CIR[7:0];
next_state=`PROC_EX_STATE_ENTRY;
end
end
11'b1000_00xx_000 : begin
/* Add Immediate word/byte to register/memory */
/* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
seq_addr_entry=`UCODE_NO_INSTRUCTION;
`start_aligning_instruction
opcode_size=1;
has_operands=1;
Wbit=CIR[8:8];
Sbit=CIR[9:9];
MOD=2'b11;
in_alu1_sel1=2'b00;
in_alu1_sel2=2'b01;
out_alu1_sel={1'b0,MOD};
reg_read_port2_addr={Wbit,RM};
reg_write_addr={Wbit,RM};
ALU_1OP=`ALU_OP_ADD;
next_state=`PROC_DE_LOAD_16_PARAM;
if(Wbit==1)
next_state=`PROC_DE_LOAD_16_PARAM;
else begin
`invalid_instruction /*do 8bit loads*/
end
end
11'b1000_00xx_111 : begin
/* CMP - compare Immediate with register / memory */
/* 1 0 0 0 0 0 S W | MOD 1 1 1 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
seq_addr_entry=`UCODE_NO_INSTRUCTION;
opcode_size=1;
has_operands=1;
Wbit=CIR[8:8];
Sbit=CIR[9:9];
MOD=CIR[7:6];
RM=CIR[2:0];
if(((Wbit==1)&&(Sbit==1))||Wbit==0)begin
`start_unaligning_instruction
end else begin
`invalid_instruction;
end
if(MOD==2'b11)begin
in_alu1_sel1=2'b00;
in_alu1_sel2=2'b01;
reg_read_port2_addr={Wbit,RM};
out_alu1_sel=3'b100;
ALU_1OP=`ALU_OP_SUB;
next_state=`PROC_DE_LOAD_8_PARAM;
end else begin
`invalid_instruction
end
end
11'b1011_0xxx_xxx : begin
/* MOV - Move Immediate byte to register */
/* 1 0 1 1 W REG | DATA | DATA if W |*/
seq_addr_entry=`UCODE_NO_INSTRUCTION;
`start_aligning_instruction
has_operands=1;
Wbit=CIR[11:11]; /* IS 0 */
opcode_size=0;
MOD=2'b11;
in_alu1_sel1=2'b00;
in_alu1_sel2=2'b00;
out_alu1_sel=3'b011;
reg_write_addr={1'b0,CIR[10:8]};
PARAM1[7:0]=CIR[7:0];
PARAM2=0;
ALU_1OP=`ALU_OP_ADD;
next_state=`PROC_EX_STATE_ENTRY;
end
11'b1011_1xxx_xxx : begin
/*MOV - Move Immediate word to register*/
seq_addr_entry=`UCODE_NO_INSTRUCTION;
`start_unaligning_instruction
has_operands=1;
Wbit=CIR[11:11]; /*IS 1 */
opcode_size=0;
MOD=2'b11;
in_alu1_sel1=2'b00;
in_alu1_sel2=2'b00;
out_alu1_sel=3'b011;
reg_write_addr={1'b1,CIR[10:8]};
ALU_1OP=`ALU_OP_ADD;
PARAM2=0;
next_state=`PROC_DE_LOAD_16_PARAM;
end
11'b1000_10xx_xxx : begin
/* MOV - Reg/Mem to/from register */
/* 1 0 0 0 1 0 D W | MOD REG RM | < DISP LO > | < DISP HI > |*/
seq_addr_entry=`UCODE_NO_INSTRUCTION;
has_operands=0;
`start_aligning_instruction
opcode_size=1;
MOD=CIR[7:6];
RM=CIR[2:0];
Wbit=CIR[8:8];
in_alu1_sel2=2'b00;
if(CIR[9:9] == 1)begin
/* Mem/Reg to reg */
if(MOD==2'b11)begin
/*Reg to Reg*/
in_alu1_sel1=2'b01;
reg_read_port1_addr={Wbit,RM};
next_state=`PROC_EX_STATE_ENTRY;
end else begin
/*Mem to Reg*/
in_alu1_sel1=2'b00;
next_state=`RPOC_MEMIO_READ;
end
out_alu1_sel=3'b011;
reg_write_addr={Wbit,CIR[5:3]};
end else begin
/* Reg to Mem/Reg */
if(MOD==2'b11)begin
/*Reg to Reg*/
in_alu1_sel1=2'b01;
out_alu1_sel=3'b011;
reg_write_addr={Wbit,RM};
next_state=`PROC_EX_STATE_ENTRY;
end else begin
/*Reg to Mem*/
in_alu1_sel1=2'b00;
reg_read_port1_addr={Wbit,CIR[5:3]};
out_alu1_sel={1'b0,MOD};
next_state=`PROC_DE_LOAD_REG_TO_PARAM;
end
reg_read_port1_addr={Wbit,CIR[5:3]};
end
ALU_1OP=`ALU_OP_ADD;
PARAM2=0;
end
11'b0100_xxxx_xxx:begin//DEC
/* DEC - Decrement Register */
/* | 0 1 0 0 1 REG | */
/* INC - Increment Register */
/* | 0 1 0 0 0 REG | */
seq_addr_entry=`UCODE_NO_INSTRUCTION;
has_operands=0;
opcode_size=0;
`start_unaligning_instruction
Wbit=1;
in_alu1_sel1=2'b01;
in_alu1_sel2=2'b00;
out_alu1_sel=3'b011;
MOD=2'b11;
PARAM2=1;
reg_read_port1_addr={1'b1,CIR[10:8]};
reg_write_addr={1'b1,CIR[10:8]};
if(CIR[11:11]==0)
ALU_1OP=`ALU_OP_ADD;
else
ALU_1OP=`ALU_OP_SUB;
next_state=`PROC_EX_STATE_ENTRY;
end
11'b1111_111x_00x : begin
/* INC - Register/Memory */
/* 1 1 1 1 1 1 1 W | MOD 0 0 0 R/M | < DISP LO> | < DISP HI> */
/* DEC - Register/Memory */
/* 1 1 1 1 1 1 1 W | MOD 0 0 1 R/M | < DISP LO> | < DISP HI> */
seq_addr_entry=`UCODE_NO_INSTRUCTION;
has_operands=1;
opcode_size=1;
`start_aligning_instruction
Wbit=CIR[8:8];
MOD=CIR[7:6];
RM=CIR[2:0];
in_alu1_sel1=(MOD==2'b11)? 2'b01 : 2'b00;
in_alu1_sel2=2'b00;/* number 1 */
PARAM2=1;
out_alu1_sel={1'b0,MOD};
/*in case MOD=11 */
reg_read_port1_addr={1'b0,RM};
reg_write_addr={1'b0,RM};
ALU_1OP=(CIR[3:3]==1)?`ALU_OP_SUB:`ALU_OP_ADD;
if ( MOD == 2'b11 )
next_state=`PROC_EX_STATE_ENTRY;
else
next_state=`RPOC_MEMIO_READ;
end
11'b1111_0100_xxx : begin
/* HLT - Halt */
/* 1 1 1 1 0 1 0 0 | */
seq_addr_entry=`UCODE_NO_INSTRUCTION;
has_operands=0;
opcode_size=0;
`start_unaligning_instruction
MOD=2'b11;
HALT=1;
next_state=`PROC_HALT_STATE;
end
11'b0011_110x_xxx : begin
/* CMP - Compare Immediate with accumulator */
/* 0 0 1 1 1 1 0 W | DATA | DATA if W |*/
/* */
/* NOTE: 8086 doc doesn't show the third byte but the */
/* W flag and my assembler seem to disagree */
seq_addr_entry=`UCODE_NO_INSTRUCTION;
Wbit=CIR[8:8];
opcode_size=0;
has_operands=1;
if(Wbit)
`start_unaligning_instruction
else
`start_aligning_instruction
MOD=2'b11;
in_alu1_sel1=2'b00;
in_alu1_sel2=2'b01;
reg_read_port2_addr={Wbit,3'b000};
out_alu1_sel=3'b100;
ALU_1OP=`ALU_OP_SUB;
if(Wbit==1)
next_state=`PROC_DE_LOAD_16_PARAM;
else begin
PARAM1[7:0]=CIR[7:0];
next_state=`PROC_EX_STATE_ENTRY;
end
end
11'b0111_xxxx_xxx:begin
/* Conditional relative jumps */
/* JE/JZ - Jump on Zero */
/* 0 1 1 1 0 1 0 0 | IP-INC8 |*/
/* JS - Jump on Sign */
/* 0 1 1 1 1 0 0 0 | IP-INC8 |*/
/* JNS -Jump on not Sign */
/* 0 1 1 1 1 0 0 1 | IP-INC8 |*/
/* .... */
seq_addr_entry=`UCODE_NO_INSTRUCTION;
has_operands=1;
`start_aligning_instruction
Wbit=1;
opcode_size=0;
in_alu1_sel1=2'b10;
in_alu1_sel2=2'b00;
PARAM2={{8{CIR[7:7]}},CIR[7:0]};
ALU_1OP=`ALU_OP_ADD_SIGNED_B;
out_alu1_sel=3'b101;
case(CIR[11:9])
3'b000: begin
/* Jump on (not) Overflow */
if(FLAGS[11:11]==CIR[8:8])
next_state=`PROC_IF_STATE_ENTRY;
else begin
next_state=`PROC_EX_STATE_ENTRY;
end
end
3'b010: begin
/* Jump on (not) Zero */
if(FLAGS[6:6]==CIR[8:8])
next_state=`PROC_IF_STATE_ENTRY;
else
next_state=`PROC_EX_STATE_ENTRY;
end
3'b100: begin
/* Jump on (not) Sign */
if(FLAGS[7:7]==CIR[8:8])
next_state=`PROC_IF_STATE_ENTRY;
else
next_state=`PROC_EX_STATE_ENTRY;
end
3'b101: begin
/* Jump on (not) Parity */
if(FLAGS[2:2]==CIR[8:8])
next_state=`PROC_IF_STATE_ENTRY;
else
next_state=`PROC_EX_STATE_ENTRY;
end
default:begin
`invalid_instruction; /*We don't support that condition*/
end
endcase
end
11'b1110_1011_xxx:begin
/* JMP - Unconditional jump direct within segment (short) */
/* | 1 1 1 0 1 0 1 1 | IP-INC-LO | */
seq_addr_entry=`UCODE_NO_INSTRUCTION;
`start_aligning_instruction
opcode_size=0;
has_operands=1;
Wbit=1;
in_alu1_sel1=2'b10;
in_alu1_sel2=2'b00;
PARAM2={{8{CIR[7:7]}},CIR[7:0]};
ALU_1OP=`ALU_OP_ADD_SIGNED_B;
out_alu1_sel=3'b101;
next_state=`PROC_EX_STATE_ENTRY;
end
11'b1100_1101_xxx:begin
/* INT - execute interrupt handler */
/* 1 1 0 0 1 1 0 1 | DATA |*/
seq_addr_entry=`UCODE_NO_INSTRUCTION;
has_operands=1;
opcode_size=0;
`start_aligning_instruction
/* Emulate MS-DOS print routines */
if(CIR[7:0]==8'h21 && register_file.registers[0][15:8]==8'h02)begin
$write("%s" ,register_file.registers[2][7:0]); /*TODO:Could trigger erroneously while CIR is not final*/
end
next_state=`PROC_IF_STATE_ENTRY;
end
11'b11101000_xxx:begin
/* CALL - Direct call within segment */
/* 1 1 1 0 1 0 0 0 | IP-INC-LO | IP-INC-HI |*/
// Microcode instruction
`start_unaligning_instruction
opcode_size=0;
has_operands=1;
Wbit=1;
Sbit=1;
PARAM2=2; //substract from sp
seq_addr_entry=`UCODE_CALL_ENTRY;
end
default:begin
`invalid_instruction
end
endcase
end else begin
/*Microcode output*/
//Sbit, Wbit, opcode_size and the others are still latched
//from when we ordered the switch to microcode
seq_addr_entry=ucode_data[5:0];
case(ucode_data[7:6])
2'b00: next_state=`PROC_EX_STATE_ENTRY;
2'b01: next_state=`PROC_DE_LOAD_16_PARAM;
2'b10: next_state=`PROC_DE_LOAD_8_PARAM;
2'b11: next_state=`PROC_DE_LOAD_REG_TO_PARAM;
endcase
reg_write_addr=ucode_data[11:8 ];
in_alu1_sel1 =ucode_data[13:12];
in_alu1_sel2 =ucode_data[15:14];
out_alu1_sel =ucode_data[18:16];
/*1:1 map essentially but I want to keep the spec for these bits seperate
* from the alu op select bits*/
case(ucode_data[21:19])
3'b000: ALU_1OP=`ALU_OP_ADD;
3'b001: ALU_1OP=`ALU_OP_SUB;
3'b010: ALU_1OP=`ALU_OP_AND;
3'b011: ALU_1OP=`ALU_OP_OR;
3'b100: ALU_1OP=`ALU_OP_XOR;
3'b101: ALU_1OP=`ALU_OP_ADD_SIGNED_B;
endcase
reg_read_port1_addr=ucode_data[25:22];
end
end
endmodule