/* ucode.txt - The contents of the microcode rom for the 9086 cpu

   This file is part of the 9086 project.

   Copyright (c) 2023 Efthymios Kritikos

   This program is free software: you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation, either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

//wbo: Wbit overwrite, {VALUE,ENABLE}. ex 11 would force one, 10 wouldn't do anything
//
//krs: Keep registers, selects weather the register port 1 and/or 2
//     addresses is set on that microcoded instruction or kept as it
//     was before allowing for registers to be parameterised.
//       {Register_write_port,Register_port2, Register_port1}
//
//rr2: reg_read_port2_addr
//
//imd: IN_MOD
//
//rr1: reg_read_port1_addr
//
//a1f: ALU 1 operation (function)
//    000:ALU_OP_ADD
//    001:ALU_OP_SUB
//    010:ALU_OP_AND
//    011:ALU_OP_OR
//    100:ALU_OP_XOR
//    101:ALU_OP_ADD_SIGNED_B
//    110:ALU_OP_SUB_REVERSE
//
//a1o: OUT_MOD. Handled in `PROC_EX_STATE_EXIT
//
//a12: In ALU 1 sel 2
//
//a11: In ALU 1 sel 1
//
//rwa: Register Write Address
//
//nxs: Next State
//     00: PROC_EX_STATE_ENTRY
//     01: PROC_DE_LOAD_16_PARAM
//     10: PROC_DE_LOAD_8_PARAM
//     11: PROC_MEMIO_READ
//
//Nxt M: Next microcode address

@000 0000_000_000__00__00_0000__00_000000

//   36  34  32   28  25   21  18  15  13  11   7   5    0
// CALL
//   wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
@001 _00_000_0000_011_1100_001_011__00__01_1100__01_000010 // ALU_1: SP           ALU_2: PARAM2 (2) ALU_OP:SUB  ALU_out: SP   (also fetch the opcode argument to PARAM1)
@002 _00_000_0000_011_zzzz_000_110__10__11_zzzz__00_000011 // ALU_1: 0            ALU_2: PC         ALU_OP:ADD  ALU_out: [SP]
@003 _00_000_0000_011_zzzz_000_101__10__00_zzzz__00_000000 // ALU_1: PARAM1 (arg) ALU_2: PC         ALU_OP:ADD  ALU_out: PC

// RET
//   wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
@004 _00_000_0000_110_zzzz_000_101__00__11_zzzz__11_000101 // ALU_1: 0           ALU_2: PARAM2 ([SP]) ALU_OP:ADD  ALU_out: PC (also read [SP] to PARAM2)
@005 _00_000_1100_011_0000_000_011__01__00_1100__00_000000 // ALU_1: PARAM1 (2)  ALU_2: SP            ALU_OP:ADD  ALU_out: SP

// STOS
//   wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
@006 _00_000_1000_011_zzzz_000_000__01__11_zzzz__00_000111 // ALU_1: 0   ALU_2: AX           ALU_OP:ADD  ALU_out: [DI]
@007 _11_000_zzzz_011_1111_000_011__00__01_1111__00_000000 // ALU_1: DI  ALU_2: PARAM2 (2)   ALU_OP:ADD  ALU_OUT: DI

// PUSH
//   wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
@008 _00_010_0000_011_1100_001_011__00__01_1100__00_001001 // ALU_1: SP  ALU_2: PARAM2 (2) ALU_OP:SUB  ALU_out: SP   (also fetch the opcode argument to PARAM1)
@009 _00_010_0000_011_zzzz_000_110__01__11_zzzz__00_000000 // ALU_1: 0   ALU_2: REG        ALU_OP:ADD  ALU_out: [SP]

// POP
//   wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
@00a _00_100_0000_110_zzzz_011_011__00__11_zzzz__11_001011 // ALU_1: 0           ALU_2: PARAM2 ([SP])    ALU_OP:ADD   ALU_out: REG
@00b _00_000_1100_011_0000_000_011__01__00_1100__00_000000 // ALU_1: PARAM1 (2)  ALU_2: SP               ALU_OP:ADD   ALU_out: SP