/* ascii_to_HD44780_driver.v - driver that takes in ascii and outputs control
   sequences for an HD44780 display

   This file is part of the 9086 project.

   Copyright (c) 2023 Efthymios Kritikos

   This program is free software: you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation, either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

module ascii_to_HD44780_driver (
	/* system */
	input wire clock,
	input wire rst_n,

	/* Data Input */
	output reg in_data_ready=0,
	input data_write_req,
	input [7:0] in_ascii_data,

	/* write circuitry */
	input wire done_writing,
	output reg write_req=0,
	output reg [3:0] data,
	output reg cmd_data=0
);

initial begin
	init_cmd_data[ 0] = 4'h3;
	init_cmd_data[ 1] = 4'h3;
	init_cmd_data[ 2] = 4'h3;
	init_cmd_data[ 3] = 4'h2;
	init_cmd_data[ 4] = 4'h2; //0x28
	init_cmd_data[ 5] = 4'h8;
	init_cmd_data[ 6] = 4'h0; //0x07
	init_cmd_data[ 7] = 4'h7;
	init_cmd_data[ 8] = 4'h0; //0x0C
	init_cmd_data[ 9] = 4'hC;
	init_cmd_data[10] = 4'h0; //0x01
	init_cmd_data[11] = 4'h1;
	init_cmd_data[12] = 4'h0; //0x06
	init_cmd_data[13] = 4'h6;
	init_cmd_data[14] = 4'h0; // 0x02
	init_cmd_data[15] = 4'h2;
end

reg [4:0] init_seq=0;
reg [5:0] data_write_wait_counter = 0;

reg [3:0] init_cmd_data [15:0];

reg byte_n=0;

reg data_write_latch=0;
reg [7:0]print_data;

always @(posedge clock,negedge rst_n) begin
	if(rst_n==0)begin
		in_data_ready<=0;
		write_req<=1'b0;
		init_seq<=5'd0;
		data_write_wait_counter<=6'd0;
		byte_n<=1'b0;
		cmd_data<=1'b0;
	end else if(done_writing)begin
		if(init_seq!=5'd16&&data_write_wait_counter==6'd0)begin
			data<=init_cmd_data[init_seq[3:0]];
			init_seq<=init_seq+5'd1;
			write_req<=1'b1;
			data_write_wait_counter<=6'd50;
			in_data_ready<=0;
		end else if (data_write_wait_counter!=6'd0) begin
			data_write_wait_counter<=data_write_wait_counter-6'd1;
			write_req<=1'b0;
			in_data_ready<=0;
		end else if(data_write_req==1&&data_write_latch==0)begin
			data_write_latch<=1;
			print_data<=in_ascii_data;
			in_data_ready<=0;
			byte_n<=0;
		end else if(data_write_latch&byte_n==0)begin
			data<=print_data[7:4];
			write_req<=1'b1;
			data_write_wait_counter<=6'd50;
			byte_n<=1;
		end else if(data_write_latch&byte_n==1)begin
			data<=print_data[3:0];
			write_req<=1'b1;
			data_write_wait_counter<=6'd50;
			byte_n<=0;
			data_write_latch<=0;
		end else begin
			cmd_data<=1;
			in_data_ready<=1;
		end
	end else begin
		write_req<=1'b0;
		in_data_ready<=0;
	end
end



endmodule